Texas Instruments OMAP5912 Reference Manual page 431

Reset Architecture
Table 4. OMAP 3.2 Resets (Continued)
Components Type
ETM MPU
MPU timer 1 MPU
MPU timer 2 MPU
MPU timer 3 MPU
MPU WD timer MPU
MPU INTH MPU
LCD controller MPU
DSP DSP
DSP MMU DSP
DSP timer 1 DSP
DSP timer 2 DSP
DSP timer 3 DSP
DSP WD timer DSP
DSP INTIF DSP
DSP INTH DSP
Mailbox
MPUI
System DMA MPU
controller
†
DSP-MMU SW reset bit in CNTL_REG of DSP-MMU module must also be set correctly for DSP-MMU to be reset.
‡
SDRAM is in self-refresh; some of the registers controlled by SDRAM FSM do not reset.
§
See Table 3 for a listing of all cold/warm resets.
MPU_RST
Note: DPLL is reset by
14 Initialization
Cold Warm DSP WD
Resets Resets
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes † Yes †
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
or 32-kHz WD. Other warm resets do not reset the DPLL.
MPU DSP Core
Reset Software Software
Reset
No No
No No
No No
No No
No No
No No
No No
Yes No
DSP core
EMIF config
regs and
MPUI control
No No
Yes No
Yes No
Yes No
Yes No
Yes No
Yes No
No No
No No
No No
DSP Software
Reset
Reset
No No
No No
No No
No No
No No
No No
No No
Yes Yes
Only EMIF con-
only, not fig regs and
MPUI control
logic in DSP, not
DSP core
logic
No No
No No
No No
No No
No No
No No
No No
No No
No No
No No
SPRU752B