Texas Instruments OMAP5912 Reference Manual page 190

Clock Generation and Reset Management
4.2.5 Traffic Controller Clock Domain
132 OMAP3.2 Subsystem
timers. At reset, the clock issued from the DPLL is selected but the timer
clocks are inactive.
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DSP Level 1 and 2.0 interrupt handlers (DSP_INTH_CK)
DSP interrupt handlers are supplied with CK_GEN2 divided by 2.
Even when the DSP is not in idle mode, you have the option of individually
disabling these subdomains using the DSP_IDLECT2 register. This allows
significant power saving when a module is not in use.
The DPLL output frequency, which drives the traffic controller, generates the
traffic controller clock (TC_CK). This TC_CK feeds the traffic controller, the
OCP initiator port (OCP-I), the OCP Target1 (OCP-T1) and OCP Target2
(OCP-T2) ports, the system DMA controller, the LCD controller, the MPUI port
interface, and the MPU TIPB bridge. TC1_CK and TC2_CK are then
broadcast outside the OMAP platform; they are identical to TC_CK and can
be powered down independently in power saving options.
The TC clock domain is divided into two subdomains:
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Traffic controller, OCP-I port, OCP-T1 and OCP-T2 ports, MPUI port
interface, system DMA controller, and MPU TIPB bridges.
The clock signal driving these modules is basically the same as the
TC_CK, except that it can be gated independently of TC_CK.
You can program the divide-down TCDIV bits of the ARM_CKCTL register
to have the CK_GEN3 further divided by 2, 4, or 8 to generate the TC_CK.
At reset, the highest frequency (divided by 1) is selected and TC_CK =
CK_REF.
At reset, the MPUI port interface clock and the system DMA controller
clock are inactive, while the OCP-I, OCP-T1, and OCP-T2 port clocks, TC
clocks, and MPU TIPB bridge are active.
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LCD controller
You can program the divide-down LCDDIV bits of the ARM_CKCTL regis-
ter to have CK_GEN3 further divided by 2, 4, or 8 to generate the LCD con-
troller clock. At reset, the highest frequency (divided by 1) is selected but
the LCD controller clock is inactive.
These traffic controller subdomain clocks can be disabled even if the MPU,
DSP, or TC are not in idle mode using the ARM_IDLECT2 register.
The DMA needs a free-running clock supplied to the external LCD controller
(SoSSI) even when the DMA clock is turned off so that the LCD controller can
SPRU749A