Texas Instruments OMAP5912 Reference Manual page 1121

Multimedia processor device overview and architecture

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I2C Multimaster Peripheral

C Multimaster Peripheral

C System Overview

Functional Overview

Serial Interfaces

The multimaster I

C peripheral provides an interface between a local host (LH)

such as an MPU, MIPS, or DSP processor and any I

that connects via the I

bus can serially transmit/receive up to 8-bit data to/from the LH device through

the two-wire I

C interface.

C peripheral supports any slave or master I

Figure 17 shows the example of a system with multiple I

in which the I

C serial ports are connected together for a two-way transfer from

one device to other devices.

C bus is a multimaster bus. The I

mode that allows more than one device capable of controlling the bus to be

connected to it. Each I

address and can operate as either transmitter or receiver, according to the

function of the device. In addition to being a transmitter or receiver, a device

connected to the I

C bus can also be considered as master or slave when

performing data transfers. A master device is a device that initiates a data

transfer on the bus and generates the clock signals to permit that transfer.

During this transfer, any device addressed by this master is considered a

C serial bus. External components attached to the I

C controller supports the multimaster

C device, including the DSP, is recognized by a unique

C-bus-compatible device

C-compatible device.

C compatible devices

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