Texas Instruments OMAP5912 Reference Manual page 858

Multimedia processor device overview and architecture

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Memory Interfaces for the EMIFS

Table 13. Supported Operations on NFMCs (Continued)

Supported Operations

Block erase multiple

Read status multiple

Note: This table summarizes the supported operations for the current NFMCs. These operations may change in the fu-

ture when new NFMCs are introduced in the market. To program new NFMCs, refer to the NFMC specifications from

NAND Flash Registers

Table 14. Register Mapping

Reg1_value (most significant word16)

Reg1_value (least significant word16)

Reg2_value (most significant word16)

Reg2_value (least significant word16)

Table 15. NAND Flash Registers

NND_REVISION

NND_ADDR_SRC

All reserved bits must be written with 0.

Memory Interfaces

For the mapping of the register, the representation below is used. Each

the least significant word16.

Table 15 lists the NAND flash registers. Table 16 through Table 46

describe the register bits.

Base Address = 0xFFFB CC00

Indicates the current revision number of the NFC

Indicates the location where a read or program(write)

operation is to be performed

Contains the byte address of the location in the NFMC from

which data is read or written by accessing the NAND

controller access register (NND_ACCESS).

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