Texas Instruments OMAP5912 Reference Manual page 208

Clock Generation and Reset Management
Table 67. Master Software Reset Register (ARM_RSTCT1) (Continued)
Bit Name
1 DSP_EN
0 ARM_RST
Note: Writing the DSP_EN bit to 0 and ARM_RST bit to 1 together initiates a global software reset.
Table 68. Peripherals Reset Register (ARM_RSTCT2)
Bit Name
31:1 RESERVED
0 PER_EN
150 OMAP3.2 Subsystem
Base Address = 0xFFFE CE00, Offset = 0x10
Function
Resets the DSP.
0: Resets the DSP, excluding the configuration
setting. The reset state is maintained as long as this
bit is asserted low.
1: The DSP is enabled. After a global reset, this bit
must be set to 1 in order to enable the DSP megacell.
Resets the MPU. This bit is always read 0
0: The MPU clock domain is enabled.
1: Reset the MPU. Once set to 1 by the MPU, this bit
returns to 0 on the next cycles
Base Address = 0xFFFE CE00, Offset = 0x14
Function
Reading these bits gives undefined values. Writing to them
has no effect.
MPU Peripheral reset. Resets and/or enables the external
peripherals connected to MPU TIPB (controls 3.2
ARMPER_nRST).
0: Resets MPU peripherals
1: Enables MPU peripherals
R/W Reset
R/W 0
R/W 0
R/W Reset
R/W 0x0000
R/W 0
SPRU749A