Dsp (Mgs3) Clocks Management; Global Power Management - Texas Instruments OMAP5912 Reference Manual

3.2.3

DSP (MGS3) Clocks Management

Global Power Management

Table 43. Idle Configuration Register (ICR)
MPU Base Address (byte) = 0xE100 0000, DSP Base Address (word) = 0x00 0000, Offset = 0x01 (word)
Bit Name
15:8 Reserved
7 RSV
SPRU753A
Clock subdomain control is done by software write to the CLKRST registers:
-
ARM_CKCTL
-
ARM_IDLECT1
-
ARM_IDLECT2
-
ARM_SYSST
-
DSP_CKCTL
-
DSP_IDLECT1
-
DSP_IDLECT2
-
DSP_SYSST
As shown in Figure 21, the clock reference to build all other clocks is provided
and controlled by the ULPD (ultralow-power device) module.
The ULPD module performs several functions, which can be divided into three
groups:
-
Power-mode control
-
Clock reference management and calibration
-
External clocks management
The ULPD can manage three principal OMAP 5912 power states: awake, big
sleep, and deep sleep.
ULPD management directly affects activation or deactivation of the CLKREF
clock.
Note:
CLKRST static configuration affects ULPD dynamic-power mode
mechanisms.
Power can be globally managed by the idle configuration register (ICR)
located in the TIPB bridge.
Function
Reserved
Reserved idle domain.
Power Management User Services
R/W *
R
R/W
Power Management
Reset
0
0
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