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Table 29. NAND Controller Status Register (NND_STATUS)
Bit
Name
31-4
Reserved
3
FIFO_EMPTY
2
FIFO_FULL
1
COUNT_ZERO
0
READY_
EVENT
SPRU756A
These masks are ANDed with the corresponding bits in the NND_STATUS
register. Then, all of these contributions are ORed again to form the global
interrupt at the boundary of the NFC.
Description
Reserved
When FIFO is empty, event is pending and this bit is 1.
When FIFO is full, event is pending and this bit is 1.
When internal counter reaches zero, event is pending and this bit is 1.
When R/B_ goes from 0 to 1, event is pending and this bit is 1.
All pending events sources are active high. Before they can be active, events
must be unmasked by writing a 1 in the corresponding mask in the
NND_MASK. For example, if READY_EVENT is 1 (pending interrupt) and
MSK_READY is 1, then the interrupt at the boundary of the NFC is active low.
A reset (resetn going low) or a soft reset clears all interrupts. To clear a pending
event, a 1 must be written in the corresponding event source. When there is
an interrupt, the software can read this register to determine which event is
active.
-
Bit 0: This READY_EVENT bit can be masked with the corresponding
MSK_EVENT bit in the NND_MASK register. This bit reflects the status of
an active event in different cases:
J
For a read operation after the address has been sent to the NFMC,
there is a latency time before the data is ready. This READY_EVENT
bit is set when the Ready/Busy_ pin goes back to high, indicating that
data can be read.
J
For a program operation, the READY_EVENT bit is set when the
programming is finished.
J
For an erase operation, the READY_EVENT bit is set when the NFMC
is finished erasing the selected block.
It is the responsibility of the software to clear this bit, as described in Table 30.
Memory Interfaces for the EMIFS
Memory Interfaces
61
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