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Interrupt Handler Software
Table 31. DSP Interrupt Sequence
Step
One or several interrupts occur
that set the corresponding bits in
DSP_ITR register
Processing interrupt
Finish the interrupt
4.1.6
Interrupt Handler Software
4.1.7
Edge-Triggered Interrupts
46
Interrupts
Interrupt Handler Action
If one active interrupt occurs and
the IRQ is not already active, the
interrupt handler sends an IRQ.
If several active interrupts occur,
the interrupt handler must locate
the interrupt with the highest
priority. If an IRQ is not already
active, the interrupt handler sends
an IRQ.
When the IRQ is sent, the
DSP_SIR_IRQ is updated and the
priority resolver is reset.
To process edge-triggered and level-sensitive interrupts correctly, the
following sequences must occur in the system. Here the sequence is
described only for the IRQ interrupt; the FIQ sequence is exactly identical.
1) The DSP interrupt handler module receives one or more incoming
interrupts from outside OMAP and registers it in the DSP interrupt register
(DSP_ITR).
2) The DSP interrupt handler determines the highest priority interrupt and
puts it in the N_IRQ register, which is not seen by software.
DSP Action
The DSP must read the
DSP_SIR_IRQ to determine the
interrupt line being serviced. Then
the DSP runs the corresponding
subroutine.
The DSP must first clear the
interrupt bit in the DSP_ITR (by
writing a 0 in the corresponding bit
or by reading the DSP_SIR_IRQ).
For a level-sensitive interrupt, the
level must be removed for the next
interrupt to occur.
Sets the NEW_IRQ_AGR of the
DSP_CONTROL_REG to reset
IRQ output and the
DSP_SIR_IRQ, thus allowing a
new IRQ generation.
SPRU757B
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