Table of Contents
Advertisement
Table 20. Interrupt Revision Register (INTH_REV)
@0xA8
Access
Default
†
DW = 32 for the MPU interrupt handler; DW = 16 for the DSP interrupt handler.
3
Level 1 MPU Interrupt Handler
3.1
Description
3.1.1
Interrupt Control and Configuration
SPRU757B
DW-1... 8
†
Reserved
R
0
This register provides the revision number of the interrupt controller block.
The MPU interrupt handler allows up to 32 hosts that generate interrupts to
connect to the MPU, which can accept only two interrupts: fast interrupt
request (FIQ) and low-priority interrupt request (IRQ). You can also program
the interrupt handler to assign different priorities and mask each interrupt, and
you can program each interrupt line to be either edge-triggered or
level-sensitive.
For power management, the clock manager can turn off the interrupt handler
functional clock. A handshaking protocol is defined for the clock and reset
module to idle or wake up the interrupt handler.
A key difference between the level 1 and level 2 MPU interrupt handler is that
there is only one set of registers, some of which differ from the level 2 handlers.
If an interrupt occurs, the ITR register stores the incoming interrupt in the
corresponding bit. When there are several incoming interrupts, the MPU
interrupt handler compares the priority level of the interrupts before sending
an IRQ or FIQ to the MPU core. The selected interrupt's number is stored in
SIR_IRQ or SIR_FIQ for the MPU to determine which interrupt service routine
to execute. Reading either of these registers by the MPU resets the
corresponding bit in ITR. The MPU can also clear each bit individually in ITR
by writing a 0 to the corresponding bits. Writing a 1 keeps its previous value.
Each incoming interrupt can be masked individually by setting the
corresponding bit in MIR to 1.
Level 1 MPU Interrupt Handler
7
6
5
4
MAJOR_REV
R
Revision dependent
3
2
1
0
MINOR_REV
R
Revision dependent
Interrupts
35
Advertisement
Chapters
Table of Contents
