Texas Instruments OMAP5912 Reference Manual page 251

Table 114. MPU to DSP Mailbox 2A Register (MPU2DSP2A)
Bit Name
15:0 MPU2DSP2A This register stores the data to be shared
Table 115. MPU to DSP Mailbox 2B Register (MPU2DSP2B)
Bit Name
15:0 MPU2DSP2B This register stores the data to be shared
Table 116. MPU to DSP Mailbox 2 Flag Register (MPU2DSP2_FLAG)
Bit Name
15:1 Reserved
0 INT
7 TIPB Bridge
SPRU749A
Base Address = 0xFFFC F000, Offset = 0x24
Function
for the MPU-to-DSP interrupt in mailbox 2.
Base Address = 0xFFFC F000, Offset = 0x28
Function
for the MPU-to-DSP interrupt in mailbox 2.
The MPU2DSP2 interrupt is generated to
DSP when this register is written. When
this register is read by DSP,
(MPU2DSP2_FLAG) is reset.
Base Address = 0xFFFC F000, Offset = 0x2C
Function
Reserved
0: No Interrupt pending
1: MPU2DSP2 interrupt generated
The TIPB bridge allows the TIPB and all peripherals connected to it to be
shared with three hosts: the MPU, the OCP initiator (OCP-I), and the system
DMA controller. The TIPB controls accesses to avoid conflicts between the
hosts, and it allows the MPU to configure the protocol parameters of the TIPB.
The TIPB bridge module is shown in Figure 44.
R/W
R/W by MPU/DMA/OCP-I
R by DSP
R/W
R/W by MPU/DMA/OCP-I
R by DSP
R/W
R
R by MPU/DMA/OCP-I
No access by DSP
OMAP3.2 Subsystem
TIPB Bridge
Reset
0x0000
Reset
0x0000
Reset
0
0
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