Texas Instruments OMAP5912 Reference Manual page 307

Multimedia processor device overview and architecture

Hide thumbs Also See for OMAP5912:

Table of Contents

Table 12. DSP Peripheral Mapping

Start Byte Address (hex)

† All other I/O memory addresses are reserved.

‡ Internal wait states for accessing peripherals are set by strobe fields in TIPB CM register (see Section 4.1, Control Mode

DSP Subsystem

An interrupt handler

MPU/DSP shared peripherals

DSP public peripherals

Two multichannel buffered serial ports (McBSPs) for synchronous

serial communications

Two multichannel serial interfaces (MCSIs)

Configuration and data registers for all peripherals reside in the DSP

subsystem I/O space, which consists of 64K-word addresses, with each

peripheral mapping into a 1K-word section of I/O memory. To read or write

these registers, you must access the DSP I/O space either through C language

constructs or by using the assembly language peripheral port register access

qualifier. See TMS320C55x DSP Mnemonic Instruction Set Reference Guide

(SPRU374D) for more details.

Table 12 shows the DSP peripheral mapping.

EMULATOR/TEST

Chapters

Table of Contents