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Table 5.
MPU Level 2 Interrupt Mapping (Continued)
Level 2 Interrupt Line
IRQ_12
IRQ_13
IRQ_14
IRQ_15
IRQ_16
IRQ_17
IRQ_18
IRQ_19
IRQ_20
IRQ_21
IRQ_22
IRQ_23
IRQ_24
IRQ_25
IRQ_26
IRQ_27
IRQ_28
IRQ_29
IRQ_30
IRQ_31
IRQ_32−
IRQ_33
IRQ_34
IRQ_35
IRQ_36
†
These IRQs are available only when the DMA is in OMAP3.2 mode (i.e. not in OMAP3.1 compatibility mode). See the Multime-
dia Processor Direct Memory Access (DMA) Support Reference Guide (literature number SPRU755) for more information.
SPRU757B
Mapping
McBSP1 TX
McBSP1 RX
UART1
UART2
MCSI1 combined TX/RX/Frame error/RST
MCSI2 combined TX/RX/Frame error/RST
Free
Reserved
USB W2FC Geni it
1-Wire
OS timer
MMC/SDIO1
32-kHz gauging IRQ/USB client wakeup IRQ
RTC periodical timer
RTC alarm
Reserved
DSP_MMU_IRQ
USB W2FC IRQ_ISO_ON
USB W2FC IRQ_NON_ISO_ON
McBSP2 RX OVERFLOW
Reserved
GPTIMER3
GPTIMER4
GPTIMER5
Interrupt Overview
Sensitivity
Edge
Edge
Level
Level
Level
Level
−−−−−
−−−−−
Level
Level
Edge
Level
Level/Edge
Edge
Level
−−−−−
Level
Level
Level
Level
−−−−−
Level
Level
Level
Interrupts
17
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