Texas Instruments OMAP5912 Reference Manual page 967

Shared Peripherals
Table 1. MPU/DSP Peripheral Access (Continued)
MPU Domain
Module MPU Start
Name
L3 OCP T1 FFFE
interface C100
OMAP5912 FFFB
TIPB switch C800
TIPB bridge FFFE
(internal) CA00
TIPB FFFE
bridge2 D300
(external)
MPUI FFFE
interface C900
DSP MMU FFFE
D200
Traffic FFFE
controller CC00
Gigacell FFFB F000 FFFB F7FF
mailbox
Mailbox FFFC F000 FFFC F7FF
DSP TIPB
MGS3
MPUI
control
register
System FFFE
DMA D800
System FFFE E000 FFFE E7FF
DMA
MPU level FFFE
1 interrupt CB00
handler
Note: The SSI and the GDD modules are on the L3-OCP2 port and thus are seen as part of memory port interface.
16 Peripheral Interconnects
MPU End MPU TIPB
Bus Type
FFFE C1FF Private
FFFB Shared
CBFF
FFFE Private
CAFF
FFFE D3FF Private
FFFE C9FF Private
FFFE D2FF Private
FFFE Private
CCFF
Shared
Shared
FFFE Private
DFFF
Private
FFFE Private
CBFF
DSP Domain
L4 Controler DSP Start
Switch
Semi-static E101 C800
Semi-static E101 F000
E100 0000
E102 0000
DSP End DSP TIPB
Bus Type
E101 Shared
CBFF
E101 Shared
F7FF
E100 Shared
07FF
E102 Shared
0003
SPRU758A