Texas Instruments OMAP5912 Reference Manual page 1046

Table 33. Timer Identification Register (TIDR)
Base Address = 0xFFFB 1400 (n * 0x800, MPU), E101 1400 (n * 0x800, DSP); n = 0...7, Offset = 0x00
Bit Name
31:8 RESERVED
7:0 TID_REV
Table 34. Timer OCP Configuration Register (TIOCP_CFG)
Base Address = 0xFFFB 1400 (n * 0x800, MPU), E101 1400 (n * 0x800, DSP); n = 0...7, Offset = 0x10
Bit Name
31:6 RESERVED
5 EMUFREE
4:3 IdleMode
2 ENAWAKEUP
SPRU759B
(LSB), 0x02 (MSB)
Function
Module HW revision number of the current timer
module: value set by hardware.
Four LSBs of TID_REV indicate a minor revision.
Four MSBs of TID_REV indicate a major revision.
A reset has no effect on value returned
(LSB), 0x12 (MSB)
Function
0: The timer is frozen in emulation mode.
1: The timer runs free.
Power management, request/acknowledge control
00: Force idle. An idle request is acknowledged
unconditionally.
01: No idle. An idle request is never
acknowledged.
10: Smart idle. Acknowledgement to an idle
request is given based on the internal activity of
the timer (see Section 4.8, Sleep Mode Request
and Acknowledge).
11: Reserved
Wake-up feature control
0: Wake-up is disabled.
1: Wake-up is enabled.
Dual-Mode Timer
R/W Reset
0x000000
R HW ID
revision
R/W Reset
0x000 0000
R/W 0
R/W 0x0
R/W 0
Timers 43