Texas Instruments OMAP5912 Reference Manual page 158

Traffic Controller
Table 19. EMIFS Chip-Select Configuration Registers
(EMIFS_CCS0, EMIFS_CCS1,...,EMIFS_CCS3) (Continued)(Continued)
Base Address = 0xFFFE CC00, Offsets = 0x10, 0x14, 0x18, 0x1C
Bit Field
18:16 RDMODE
15:12 PGWST/WE
LEN
11:8 WRWST
7:4 RDWST
3 RESERVED
2 RT
1:0 FCLKDIV
Note: The EMIFS chip-select configuration register reset values forCS0 and CS3 depend on a number of factors at reset
release time. For more details, see Section 3.2.18, EMIFS Boot Mode.
100 OMAP3.2 Subsystem
Description
Read mode select (see table below and section 3.2.1). See
section 3.2.18 for RDMODE reset value for CS0 and CS3.
Controls the wait states cycle number between accesses in
a page for asynchronous page mode. Controls the WE
pulse length during a write access.
When PGWSTEN is 0, this bit specifies both
PGWST/WELEN
When PGWSTEN is 1, this bit specifies only WELEN
Controls the wait states cycle number for write operation.
Controls the wait states cycle number for asynchronous
read operation and the initial idle time for asynchronous
read page mode and synchronous read mode.
Reserved. Writing to this bit has no effect. Reading it
returns undefined value.
Enable the read retimed protocol. This bit may be 1 only
in RDMODE 4,5 and 7 only. The system will hang if the
retiming bit is set in other modes. See section 3.2.18 for
RT reset value for CS0 and CS3.
0: Non retimed protocol.
1: retimed protocol.
Controls the TC_CK divider. REF_CLK.
00: REF_CLK = TC_CK divide by 1.
01: REF_CLK = TC_CK divide by 2.
10: REF_CLK = TC_CK divide by 4.
11: REF_CLK = TC_CK divide by 6.
See section 3.2.18 for RT reset value for CS0 and CS3.
R/W Reset
R/W See note
or 000
R/W See note
or 1111
R/W See note
or 1111
R/W See note
or 1111
R/W 1
R/W See note
or 1
R/W See note
or 11
SPRU749A