Table of Contents
Advertisement
DSP DMA
Table 107. DMA Controller Configuration Registers (Continued)
Register
DMA_CSR0
DMA_CSSA_L0
DMA_CSSA_U0
DMA_CDSA_L0
DMA_CDSA_U0
DMA_CEN0
DMA_CFN0
DMA_CSFI0
DMA_CSEI0
DMA_CSAC0
DMA_CDAC0
DMA_CDEI0
DMA_CDFI0
DMA_CSDP1
DMA_CCR1
DMA_CICR1
DMA_CSR1
DMA_CSSA_L1
DMA_CSSA_U1
DMA_CDSA_L1
DMA_CDSA_U1
DMA_CEN1
DMA_CFN1
DMA_CSFI1
150
Direct Memory Access (DMA) Support
Description
Channel 0 (Continued)
Channel 0 status
Channel 0 source start address, lower bits
Channel 0 source start address, upper bits
Channel 0 destination start address, lower bits
Channel 0 destination start address, upper bits
Channel 0 element number
Channel 0 frame number
Channel 0 source frame index
Channel 0 source element index
Channel 0 source address counter
Channel 0 destination address counter
Channel 0 destination element index
Channel 0 destination frame index
Channel 1
Channel 1 source destination parameters
Channel 1 control
Channel 1 interrupt control
Channel 1 status
Channel 1 source start address, lower bits
Channel 1 source start address, upper bits
Channel 1 destination start address, lower bits
Channel 1 destination start address, upper bits
Channel 1 element number
Channel 1 frame number
Channel 1 source frame index
Word Address
0C03h
0C04h
0C05h
0C06h
0C07h
0C08h
0C09h
0C0Ah
0C0Bh
0C0Ch
0C0Dh
0C0Eh
0C0Fh
0C20h
0C21h
0C22h
0C23h
0C24h
0C25h
0C26h
0C27h
0C28h
0C29h
0C2Ah
SPRU755B
Advertisement
Chapters
Table of Contents
