Texas Instruments OMAP5912 Reference Manual page 410

2) The frequency on the MCLK can be set accordingly: COM_RATIO_SEL[7:2]. The resulting frequency is given in
the following table:
COM_RATIO_SEL[7:2] = 0X00000, MCLK = 48 MHz
COM_RATIO_SEL[7:2] = 0X00001, MCLK = 32 MHz
COM_RATIO_SEL[7:2] = 0X00002, MCLK = 24 MHz
COM_RATIO_SEL[7:2] = 0X00003, MCLK = 19.2 MHz
COM_RATIO_SEL[7:2] = 0X00004, MCLK = 16 MHz
COM_RATIO_SEL[7:2] = 0X00005, MCLK = 13.7 MHz
COM_RATIO_SEL[7:2] = 0X00006, MCLK = 12 MHz
COM_RATIO_SEL[7:2] = 0X00007, MCLK = 9.6 MHz
COM_RATIO_SEL[7:2] = 0X00008, MCLK = 8 MHz
COM_RATIO_SEL[7:2] = 0X00009, MCLK = 6.9 MHz
COM_RATIO_SEL[7:2] = 0X000012, MCLK = 3 MHz
COM_RATIO_SEL[7:2] = 0X000032, MCLK = 1 MHz
3) EXT_48M is an external 48−MHz input clock multiplexed with GPIO4.
4) The 48 MHz from the APLL, which can be observed on CAM.D[7], if the observability mode is configured.
5) Please refer to section 5.14 for more information on the relationship between activating requests.
5.14 OMAP5912 Output Clocks
5.14.1 MCLK and MCLKREQ
SPRU751A
There are four OMAP5912 output clocks that can be used to clock external
ICs. All of these output clocks are on pins that are multiplexed with other
functions. Therefore, the appropriate pin multiplexing must be programmed by
software (e.g. MCLK is selected on ball V5, MCLKREQ is selected on ball R10,
etc.).
The hardware request for MCLK, MCLKREQ, is available on ball R10, in
multiplexing mode 0. It is active high. Using this request, the user can get the
system clock on MCLK.
To get the system clock on MCLK using a hardware request,
J
Set the CONF_MOD_COM_MCK_12_48_SEL_R bit to 0 in the
MOD_CONF_CTRL_0 register.
J
Set the COM_SYSCLK_PLLCLK_SEL bit to 1 in the ULPD
COM_CLK_CTRL_DIV_SEL register.
J
Set the DIS_COM_MCLK_REQ
SOFT_DISABLE_REQ_REG register.
J
Set the SOFT_COM_MCKO_REQ bit to 0 in the ULPD
SOFT_REQ_REG.
Consequently, setting MCLKREQ (R10) high puts the system clock on MCLK
(V5). The software can mask out MCLKREQ, and deactivate MCLK by
changing SOFT_DIS_COM_MCLK_REQ. When the system clock is output on
OMAP5912 Clock Architecture
bit to 0 in the
Clocks
ULPD
55