Texas Instruments OMAP5912 Reference Manual page 725

Table 57. DMA Channel Source Start Address Lower Bits Register (DMA_CSSA_L)
Base Address = 0xFFFE D800, Offset Address = 0x08 + n*0x40
Bit Name
15:0 SSAL
Table 58. DMA Channel Source Start Address Upper Bits Register (DMA_CSSA_U)
Base Address = 0xFFFE D800, Offset Address = 0x0A + n*0x40
Bit Name
15:0 SSAU
Table 59. DMA Channel Destination Start Address Lower Bits Register
(DMA_CDSA_L)
Base Address = 0xFFFE D800, Offset Address = 0x0C + n*0x40
Bit Name
15:0 DSAL
SPRU755B
SYNC: Synchronization status
-
Set to 1 when a DMA request is made in a synchronized channel. When
there is a TIPB read access to DMA_CSR register, this bit returns to zero.
Sync = 1: Logical channel is servicing synchronized DMA request.
Sync = 0: Logical channel is not servicing a synchronized channel, or DMA
request has not been scheduled.
Function
Source start address, lower bits
Source start address, lower bits
-
Lower bits of the source start address, expressed in bytes. The source
start address generated by the DMA is up to a 32-bit address, made of the
concatenation of DMA_CSSA_U and DMA_CSSA_L.
Function
Source start address, upper bits
Source start address, upper bits
-
Upper bits of the source start address, expressed in bytes. The source
start address generated by the DMA is a byte address, made of concate-
nation of DMA_CSSA_U and DMA_CSSA_L.
Function
Destination start address, lower bits
Destination start address, lower bits
-
Lower bits for the destination start address, expressed in bytes. The des-
tination start address is up to a 32-bit address, made of the concatenation
of DMA_CDSA_U and DMA_CDSA_L.
Direct Memory Access (DMA) Support
System DMA
R/W Reset
R/W N/A
R/W Reset
R/W N/A
R/W Reset
R/W N/A
101