Texas Instruments OMAP5912 Reference Manual page 254

TIPB Bridge
7.1.5 Time-Out
7.1.6 Debug
7.2 Registers
196 OMAP3.2 Subsystem
handles the access to the TIPB peripheral so that the MPU is not stalled during
the access.
If the MPU/system DMA/OCP-I performs another TIPB operation when there
is a posted write, this operation must wait until the posted write is complete.
If the system DMA or OCP-I performs a read operation to the same address
as the posted write, the posted write data is not forwarded to the DMA or
OCP-I. Posted write is not supported for DMA and OCP-I accesses.
Using (ARM_RHEA_CNTL), you can enable posted write independently for
strobe 0 or strobe 1 address spaces. This provides some flexibility over which
MPU TIPB peripherals are configured for posted write. Refer to the memory
map in chapter 10 for details on strobe address space assignments.
A TIPB access time-out limits the maximum time a peripheral can stall the
processor. When starting an access on the TIPB, the time-out counter is
loaded with the value programmed in the TIMEOUT bits of (RHEA_CNTL). If
the current access is not finished when the counter reaches 0, the cycle is
aborted and an abort is generated to the MPU/system DMA/OCP-I.
The time-out value is calculated by
t = (1/f
time-out bridge_clk
where f is the traffic controller clock frequency setting.
bridge_clk
The time-out can be used in conjunction with the posted write. The counter
begins counting down when the posted write transaction has been scheduled,
and this count continues against the posted transaction even if another
transaction to the TIPB bridge occurs.
The time-out can
(ENH_RHEA_CNTL).
Debug registers are saved on the occurrence of an MPU_TIPB abort. Abort
can be caused by time-out or by size mismatch between the access word width
and the word width of the addressed peripheral.
The access address, data and error flags are saved to (DEBUG_ADDRESS),
(DEBUG_DATA_LSB),
(DEBUG_CTRL_SIGNALS).
All TIPB bridge configuration and debug registers are 16-bit registers. Write
accesses to all TIPB registers can be performed only in MPU supervisor mode.
Read accesses can be performed in MPU supervisor or user modes.
) × ((RHEA_CNTL.TIMEOUT) + 1)
be disabled using
(DEBUG_DATA_MSB),
the TIMEOUT_EN
SPRU749A
bit in
and