Texas Instruments OMAP5912 Reference Manual page 233

5.2.7 Bus Error
5.2.8 Interrupt
SPRU749A
DMA/OCP-I write accesses are released before the write completion on the
peripheral side. The MPU/system DMA/OCP-I is then free to carry on with the
next access and the posted writes run as slots become available. This
functionality can be turned off to aid in debugging, because when write posting
is enabled it becomes difficult to attribute a bus error to a particular access.
Only the MPU has full control over the posted write enable bits
(ENA_WPOST_APIRAM and ENA_WPOST_TIPB in (APIRS)). At reset,
posted write is inactive (0), but, when active, the posted write mode is selected
for memory and peripheral accesses. Posted writes do not slow down the host;
this is useful because in SAM, the DSP has the priority. When the transition
from SAM to HOM is issued, it occurs after any outstanding posted writes are
completed.
There are two sources of bus error for the MPUI port: the MPUI port itself and
the DSP TIPB bridge. (DEBUG_FLAG) stores these bus errors.
The DSP TIPB bridge limits the time allowed for any peripheral bus
transaction. The DSP TIPB bridge can terminate a peripheral bus transaction
if a predetermined period of time has elapsed and no response has been
received from the peripheral. In this case the DSP TIPB bridge issues an abort
to the MPU via the MPUI port.
The DSP TIPB bridge can also issue an abort to MPU when the MPU/system
DMA/OCP-I addresses a peripheral in the wrong mode (performing an 8-bit
access to a 16-bit peripheral or vice versa).
The MPUI port issues an abort to the MPU upon detecting an incorrect bus
transaction, such as two chip-selects being active at the same time. A second
source of bus error in the MPUI port occurs when a write-only register, such
as the interrupt register, is read. The same is true if a read-only register is
written.
The DSP can send one interrupt to the MPU. This is done by setting the
corresponding bit in (ST3) (bit 12 of status register 3 of TMS320C55x
DSP—see TMS320C55x functional specification) to active-low.
Similarly, the MPU can interrupt the DSP, and eight DSP interrupt request lines
are mapped. An interrupt is generated when the MPU writes a 0 to any of the
MCU_IRQ[7:0] bits of (APIRI). These bits are written only by the MPU or
OCP-I.
MPU and MPUI Port
OMAP3.2 Subsystem 175