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Table 6.
EMIF Fast Controlled-Delay Block Programming
86
OMAP3.2 Subsystem
When loading a value into the DLL, the DLL must be enabled (ENADLL set to
1) for the load to be effective, for at least two clock cycles.To setup the
controlled delay block for unlock mode:
-
Write into the DLL control register, with ENADLL set, LOADDLL set, delay
field set to the expected value.
-
Write into the DLL control register, with ENADLL reset, to save power.
To setup the controlled delay block for lock mode (normal mode):
-
Write into the DLL control register, with ENADLL set, LOADDLL set, Delay
field set to 128 (half range to minimize locking time).
-
Write into the DLL control register, with LOADDLL reset, to launch the
tracking process.
-
Wait for at least 336 TC clock cycles to be sure the DLL is locked, before
accessing the memory.
Once locked, the DLL can be periodically disabled under software control,
assuming this period is short compared with the voltage and temperature
variations. When disabled, the DLL counter is frozen to its current value. When
enabled again, the tracking resumes from that DLL counter value.
The delay can be fine tuned using the programmable offsets. These offsets are
6-bit signed quantities, resulting in a +31/−32 adjustment range.
Step value: 26.3 ps +/− 10 ns. This value is valid in all PVT conditions
(industrial temperature range −40 to 125 degrees, voltage range 1.35 V to 1.65
V, weak or strong process).
Table 6 provides the typical programming required for an OMAP3.2-based
device, C035 process, with a 1.8 V −3 V I/O voltage range.
Memory Type
Frequency range
DLLPhase (RD DLL/WR
DLL)
Unlock mode
Forced delay value
Read offset
Write offset
DDR 1
Mobile DDR
83−100 MHz
0−66 MHz
90/72°
x
No
Yes
x
104
8
0
−1
−18
66−100 MHz
90/72°
No
X
8
−1
SPRU749A
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