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Table 2.
Pointer Operation
2.1.1
Read Operation
SPRU756A
A, the command 0x00 is sent to the flash core. To access area B, the command
0x01 is sent. To access the spare area, the command 0x50 is sent (see
Table 2).
Command
0x00
0x01
0x50
The erase operation performs on a block basis. For the most recent NFMCs,
one block equals 32 pages, or 16K bytes. On 512M-bit and 1G-bit NFMCs,
there is also a logical array division by plane:
-
The 512M-bit has four planes, each with 1024 blocks of 32 pages per
block.
-
The 1G-bit has eight planes, each with 1024 blocks of 32 pages per block.
To be generic, most control must be done in software. Commands, for
instance, are not hard-coded because they can change in different versions
of NFMC, or new commands can be added.
There are two types of commands: one must be followed by an address (for
instance, read, program, and erase); the other does not need to be followed
by an address (for instance, read status, end of data (0x10 or 0x11) in the case
of program operation). An address register is necessary to store the starting
address (32 bits). An access to the first type of command register places the
command on the 8-bit NFMC bus and the data located in the address register
also is driven on the bus. Writing data in the second type of command register
does not issue an access to the address register. For read operation, after the
address is transmitted to the NFMC, there is a latency time to wait for the data
to be ready (typically 12 µs). The wait can be done either by an interrupt or by
polling the R/B_.
First, the command 0x00, 0x01 or 0x50 is driven on the bus with the qualifier
CLE being high. Then the start address is driven byte-by-byte with the least
significant byte first, with the qualifier ALE being high. The NFMC drives its
Ready/Busy_ (R/B_) to low. When R/B_ goes back to high, an interrupt is
asserted and data is ready to be sampled by negative pulse on RE_. An access
on the NAND controller access register (NND_ACCESS) triggers the negative
Accessed Address
0-255
256-511
512-527
Memory Interfaces for the EMIFS
Area
Area A (lower half-page)
Area B (upper half-page)
Area C (spare)
Memory Interfaces
23
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