Texas Instruments OMAP5912 Reference Manual page 848

Memory Interfaces for the EMIFS
42 Memory Interfaces
When the FIFO is full with FIFO_SIZE byte(s), the NFC signals it by asserting
low an interrupt (event FIFO_FULL is 1 and MSK_FULL is 1) and the counter
is decremented. The host can read the FIFO through the register NND_FIFO
access(es). Any read past the last byte of the FIFO returns the last byte of the
FIFO.
For instance, if the FIFO_SIZE is 16 and the pointer is on the 14
the FIFO, a 32-bit read of the FIFO returns:
Where B14 was the byte at position 14 in the FIFO, and B15 was the byte at
position 15 in the FIFO.
When the FIFO is fully read by the host, the NFC state machine can fill the
FIFO again. Active events are cleared by software by writing to the
NND_STATUS register. When the internal counter reaches zero, an interrupt
is asserted (event COUNT_ZERO is 1 and MSK_COUNT is 1), and the
prefetch is stopped. The host can also decide at any time to stop the prefetch
by writing a 0 to the prefetch bit.
-
NFC fetches the data and fills the FIFO. (Access to FIFO in that case, is
stalled.)
-
When the FIFO is full, the NFC asserts the interrupt (FIFO_FULL event
pending and MSK_FULL equals 1) and the internal counter is
decremented.
-
By host accesses to NND_FIFO, read the FIFO. The FIFO_FULL event
must be cleared by writing to NND_STATUS or a future FIFO_FULL event
will not be seen.
-
When the FIFO is empty and the counter is not 0, the NFMC triggers a new
prefetch.
-
If the counter is zero, the event COUNT_ZERO is set and interrupt is
asserted if MSK_COUNT is set and the prefetch is stopped.
-
The host clears the pending event(s) by writing to NND_STATUS of the
NFC.
When prefetch goes from 0 to 1:
-
The internal counter is loaded with the BLOCK_COUNT value of the
NND_FIFOCTRL register.
-
The FIFO is flushed. (FIFO_EMPTY event is set. Depending on the value
of MSK_EMPTY, the interrupt is asserted or not.)
[31:24] [23:16]
Data read = B15 B15
th
position of
[15:8] [7:0]
B15 B14
SPRU756A