Texas Instruments OMAP5912 Reference Manual page 596

Power Management User Services
Table 45. EMIF Global Control Register (GCR)
MPU Base Address (byte) = 0xE100 0800, DSP Base Address (word) = 0x00 0800, Offset = 0x00 (word)
Bit Name
15:11 RESERVED
10:9 MEMFREQ
8 RESERVED
7 WPE
6 RESERVED
5 MEMCEN
4 ARDYOFF
3 ARDY
2 HOLD
1 HOLDA
0 NOHOLD
78 Power Management
Function
Reserved
MEMory clock FREQuency
MEMFREQ = 00: SBSRAM and/or the SDRAM interface is
configured for 1x mode and the CLKMEM clock frequency
is equal to the DSP clock frequency
MEMFREQ = 01: SBSRAM and/or the SDRAM interface is
configured for 1/2x mode and the CLKMEM clock
frequency is equal to the DSP clock frequency divided by
2.
MEMFREQ = 10 or 11: Reserved for future clock rates.
Reserved
Write posting enable
WPE = 0, write posting is disabled (for debug).
WPE = 1, write posting is enabled.
Reserved
MEM Clock ENable
MEMCEN = 0, CLKMEM held high
MEMCEN = 1, CLKMEM enabled to clock
Async. ready off.
Value of the ARDY input.
Value of HOLD input
Value of HOLDA output
External HOLD disable
NOHOLD = 0, hold enabled
NOHOLD = 1, hold disabled
The TIPB control mode register (CMR) includes wait state bits that can be used
to set the strobe frequency of the peripherals. Table 46 defines CMR.
R/W Reset
R 0
R 0
R/W 0
R/W 0
R/W 0
R/W 1
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
SPRU753A