Texas Instruments OMAP5912 Reference Manual page 868

Memory Interfaces for the EMIFS
Table 30. How to Clear Pending Event
Table 31. NAND Controller Ready Register (NND_READY)
Bit Name
31-1 Reserved
0 READY
Table 32. NAND Controller Command Register (NND_COMMAND)
Bit Name
31-8 Reserved
7-0 COMMAND
62 Memory Interfaces
Previous Event State
0
1
1
-
Bit 1: When the NFC is either in prefetch or postwrite mode, an interrupt
is generated when the internal counter reaches zero. This interrupt is
cleared by software according to the scheme shown in Table 30. The
interrupt is active if unmasked.
-
Bit 2: When the FIFO is full, the FIFO_FULL event goes to 1 and an
interrupt is asserted if unmasked. The interrupt is cleared by software
according to the scheme shown in Table 30.
-
Bit 3: When the FIFO is empty, the FIFO_EMPTY goes to 1 and an
interrupt is asserted if unmasked. The interrupt is cleared by software
according to the scheme shown in Table 30.
-
Bits 31-4: Reserved
Reserved
Ready. When 1, NFMC is ready for next operation.
-
Bits 31-1: Reserved
-
Bit 0: This bit is the copy of the R/B_ signal coming from the NFMC
resynchronized inside the NFC. This bit polls the readiness of the NFMC.
It is impossible to write to this bit. Its value at reset is the sampled value
of the R/B_ pin.
Reserved.
Command operation code.
Read 1 (lower)
Write
1 or 0
1
0
Description
Description
Next Event State
0
0
1
Reset Type
00000000 00
SPRU756A