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Table 12. DSP Peripheral Mapping (Continued)
Start Byte Address (hex)
x 004800
x 005000
x 005800
x 006000
x 006800
x 007000
x 007800
x 008000
x 008800
x 009000
x 009800
x 00A000
x 00A800
x 00B000
x 00B800 to x 00F800
X01 0000
X01 0800
X01 0C00
X01 1000
X01 1400
X01 1800
X01 1C00
X01 2000
X01 2400
† All other I/O memory addresses are reserved.
‡ Internal wait states for accessing peripherals are set by strobe fields in TIPB CM register (see Section 4.1, Control Mode
Register).
SPRU750A
Name
Configurable (private/shared)
TIMER 1
TIMER 2
TIMER 3
WD_TIMER
DSPINT IF
Private
CLK_M2
Configurable (private/shared)
Level 2 interrupt handler 2.0
Level 2 interrupt handler 2.1
Reserved
Reserved
Reserved
Reserved
UART1
UART2
SPI
McBSP2
GPTIMER1
McBSP1
GPTIMER2
MCSI2
GPTIMER3
CS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23 to 31
0
1
1
2
2
3
3
4
4
DSP Subsystem
DSP Memory
Strobe
Strobe0/n
Stroben
Stroben
Stroben
Stroben
Stroben
Strobe0
Strobe0/n
Strobe0
Strobe0
Strobe1
Strobe1
Strobe1
Strobe1
Strobe1
Strobe1
Strobe1
Strobe1
Strobe1
45
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