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4.3.5
DPLL Idle Control
4.3.6
Chip Idle Mode, Deep Sleep Mode, and Wake-up Control
SPRU749A
with a programmable counter that delays the restart of all clocks from
FLASH.RP signal going high. The EXTPWR bit field of the ARM_EWUPCT
register permits the delay to be defined as follows:
WT
= (EXTPWR
(wake-up time)
The DPLL can be set to idle mode if only the input reference clock (CK_REF)
is needed.
The DPLL idle mode is entered when the IDLDPLL_ARM bit of the
ARM_IDLECT1 register is set to logical 1 and all of the domains that use the
DPLL clock are stopped. This means that the only domains running (domains
that use CK_REF rather than the DPLL clock) are:
-
MPU and DSP watchdog timers (CK_REF/14)
-
Internal MPU timers when ARM_TIMXO bit of the ARM_CKCTL register
is set to logical 0
-
Internal DSP timers when TIMXO bit of the DSP_CKCTL register is set to
logical 0
The DPLL idle mode entry/exit time can be significant. The input reference
clock must be active for at least 24 input clock cycles from the idle request (idle
rising edge) before the idle setup is complete. Once the idle mode is exited,
the DPLL is set in bypass mode and the output signal is valid after a maximum
of 10 input reference clock cycles. The total DPLL idle entry-to-exit sequence
takes no less than 34 reference clock cycles. Therefore, it may be preferable
not to shutdown the DPLL when MPU or DSP have to be stopped for a short
period of time or when critical operations are likely to occur (that is, DMA
transfer, interrupt handling).
The OMAP 3.2 hardware engine is considered to be in chip idle mode when
the MPU, DSP, peripherals, DPLL, and peripherals using CK_REF as their
source are stopped.
Once the procedures for MPU idle, DSP idle, traffic controller idle, and DPLL
idle have been followed, the chip idle state is reached. The following ordering
is recommended to ensure that all of the clock domains can be made idle:
J
The first domain to idle is the DSP clock domain. Ensure that the MPUI
interface has been correctly initialized, and that the API_SIZE value is
zero. Then follow the sequence for DSP idle already described
Clock Generation and Reset Management
± 1) x CK_REF
(field value)
OMAP3.2 Subsystem
(period)
139
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