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Memory Interfaces for the EMIFS
Figure 16.
Single Page Read DMA
Software sends the read command.
Software sends the address.
Reset
NND_ECC1,
NND_ECC2.
ECC 256
Software sends the Read command.
Software sends the address.
Reset
NND_ECC1,
NND_ECC2.
ECC 512
Write Operation
2.1.17
FIFO mode
Prefetch
46
Memory Interfaces
Main area
Read data from flash and
accumulate ECC in
NND_ECC1.
Read data from flash and
accumulate ECC in
NND_ECC1.
No DMA signal is generated in DMA program operation.
After the host programs the address of the page to read, and the command
read is sent, the host enables the FIFO prefetch bit and enables DMA in
system DMA. The internal counter is loaded with the BLOCK_COUNT value
of the NND_FIFOCTRL register, and the DMA request is driven high (see
Figure 17).
The NFMC enters its busy mode as indicated by the R/B_ terminal. When the
NFMC is ready, the NFC starts fetching one FIFO_SIZE byte(s) of data and
begins to fill the NFC internal FIFO. While the FIFO is being loaded with data
from NFMC, access to data, address, and command registers is stalled.
When the FIFO is full with FIFO_SIZE byte(s), the NFC signals it by asserting
low the DMA request, and the internal counter is decremented by one. The
DMA can read the FIFO through access(es) to the NND_FIFO register. Any
spare
Read data from flash and
accumulate ECC in
NND_ECC2.
DMA ends.
Cleared by software
Main area
spare
DMA ends.
Cleared by software.
FldmaReqn
Flintn
The host can decide to
read the NND_ECC1 and
NND_ECC2.
ECC check done in software.
Fldmareqn
Flintn
The host can decide to
read the NND_ECC1.
ECC check done in
software.
SPRU756A
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