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System DMA
DMA LCD Channel Sharing Feature
Disabling Feature
LCD Channel Restriction
DMA LCD Channel Autoinitialization Feature
80
Direct Memory Access (DMA) Support
A(n+1) = A(n) + ES_B1/2
where:
A(n) is the byte address of element n within the transfer.
ES_B1/2 is block1/2 element size.
TB1/2 is top address for block1/2 and BB1/2 is bottom address for
block1/2.
Refer to post-increment details in section 3.2.2.
Hardware rotation is not supported in compatible mode due to restrictions on
addressing modes.
A second external LCD controller is not supported in compatible mode. Only
the OMAP3.2 embedded LCD controller is available.
The LCD channel cannot be disabled by software. However, it stops
transferring as soon as the OMAP LCD controller disables the LCD channel.
Then it restarts from the beginning again, after the LCD controller enables the
LCD channel.
In OMAP 3.1 compatible mode, it is not possible to change any bit of any LCD
channel register until a transfer has been fully completed, because no shadow
registers exist in LCD channel as in regular channels. To update registers, the
LCD_Controller must not be enabled and all pending LCD interrupts must be
processed.
The LCD channel source can only have 32-bit access from L3_OCP_T1 (Test
RAM) or EMIFF (SDRAM).
Selecting the lcd_source_port bit-field (in the DMA_LCD_CTRL register) to
binary 10 or 11 causes undefined effects.
At the end of transfer, the LCD logical channel is enabled again if
LCD_LCD_EN is set to 1 in the OMAP LCD controller. Table 31 summarizes
the autoinitialization behavior in compatible mode.
if TB1/2 ≤ A(n+1) ≤ BB1/2
SPRU755B
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