Texas Instruments OMAP5912 Reference Manual page 862

Memory Interfaces for the EMIFS
Table 20. NAND Controller Control Register (NND_CTRL) (Continued)
Bit Name
8 CHIPEN0
7 Reserved
6 ADRCNT[1]
5 ADRCNT[0]
4 A8
3 BE
2 Reserved
1 ECC_256
0 ECC_ON
Table 21. ECC Bits Operation
56 Memory Interfaces
Description
ChipEnable0. When 0, NFMC device is selected.
Reserved
Address counter for sending bytes to NFMC
Address counter for sending bytes to NFMC
When 0, bit A8 of address register is not sent to NFMC.
Switch big/little endian. 1: big endian, 0: little endian
Reserved
If 1, ECC is calculated on 256 bytes, else 512 bytes.
If 1, ECC logic is enabled.
Bit 0: When set, the ECC logic is enabled and for read or program operation,
ECC is computed and stored in the NND_ECCx registers. When ECC_ON is
set, it is impossible to write to the ECC_256 bit to avoid corrupting the ECC
logic.
ECC_ON ECC_256
0 Don't care
1 1
1 0
Bit 1: When set, ECC is accumulated on a chunk of 256 bytes or 512 bytes.
The algorithm is the same for both; only two more parities (P2048 and P2048')
are calculated. This bit must be set before enabling the ECC logic. Depending
on the value of ECC_ON (bit 0), two accesses may be needed to change the
size of the ECC calculation.
Bit 2: Reserved
Bit 3: To select between big and little endian. Depending on the access
(32-/16-/8-bit) type and this bit, the NFC packs bytes differently. For example,
assume that the NAND flash memory core contains:
-
B0 at address n
-
B1 at address n+1
-
B2 at address n+2
-
B3 at address n+3
Effect
No change (previous value)
ECC calculated on 256 bytes
ECC calculated on 512 bytes
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