Texas Instruments OMAP5912 Reference Manual page 916

Interrupt Overview
Table 5. MPU Level 2 Interrupt Mapping (Continued)
Level 2 Interrupt Line
IRQ_37
IRQ_38
IRQ_39
IRQ_40
IRQ_41
IRQ_42
IRQ_43
IRQ_44
IRQ_45
IRQ_46
IRQ_47
IRQ_48
IRQ_49
IRQ_50−
IRQ_52
IRQ_53
IRQ_54
IRQ_55
IRQ_56
IRQ_57
IRQ_58
IRQ_59
IRQ_60
IRQ_61
IRQ_62
†
These IRQs are available only when the DMA is in OMAP3.2 mode (i.e. not in OMAP3.1 compatibility mode). See the Multime-
dia Processor Direct Memory Access (DMA) Support Reference Guide (literature number SPRU755) for more information.
18 Interrupts
Mapping
GPTIMER6
GPTIMER7
GPTIMER8
IRQ1_GPIO2
IRQ1_GPIO3
MMC/SDIO2
CompactFlash
COMMRX (emulation event)
COMMTX (emulation event)
Peripheral wake up
Free
IRQ1_GPIO4
SPI
Reserved
IRQ_DMA_CH6 †
IRQ_DMA_CH7 †
IRQ_DMA_CH8 †
IRQ_DMA_CH9 †
IRQ_DMA_CH10 †
IRQ_DMA_CH11 †
IRQ_DMA_CH12 †
IRQ_DMA_CH13 †
IRQ_DMA_CH14 †
IRQ_DMA_CH15 †
Sensitivity
Level
Level
Level
Level
Level
Level
Edge
Level
Level
Level
Level
Level
Level
−−−−−
Level
Level
Level
Level
Level
Level
Level
Level
Level
Level
SPRU757B