Texas Instruments OMAP5912 Reference Manual page 222

Clock Generation and Reset Management
Table 83. DPLL Registers
Name
DPLL1_CTL_REG
DPLL2_CTL_REG
Table 84. DPLL1 Control Register (DPLL1_CTL_REG)
Bit Name
15 LS_DISABLE
14 IAI
13 IOB
†
12 TEST
† POCLKOUT[1, 2, 3] is a nongated output from clock domain[1, 2, 3]. Using the [A/D/T] CLKOUT bits, select between different
clocks used in the respective domains.
164 OMAP3.2 Subsystem
Base Address = 0xFFFE CF00
Description
DPLL1 control
DPLL2 control (all reserved)
Base Address = 0xFFFE CF00, Offset = 0x00
Function
Controls the level shifter power-down pin
0: Level shifter is in transparent mode; all signals
between the wrapper and the DPLL core are
connected
1: Level shifter is in isolated mode; the wrapper and
the DPLL core are disconnected, so the DPLL core
power supply (VDD_DPLL) can be turned off. There
is no leakage current between VDD and VDD_DPLL.
Initialize after idle.
Value of this bit must not be changed. Must be set
to 0.
Initialize on break.
When high, DPLL switches to bypass mode and
starts a new locking sequence, even if the DPLL core
indicates that it has lost the lock.
When low, DPLL continues to output the synthesized
clock, even if the core indicates it has lost the lock but
the BREAKLN is active low.
Controls the test output clock on the
DPLL_TCLKOUT pin as given below:
0: DPLL_TCLKOUT = DPLL1 output clock when in
test mode.
1: DPLL_TCLKOUT = DPLL1 output clock divided by
32 when in test mode.
X: DPLL_TCLKOUT = 0 when not in test mode.
R/W Offset
R/W 0x00
R 0x100
R/W Reset
R/W 0
R/W 0
R/W 1
R/W 0
SPRU749A