Texas Instruments OMAP5912 Reference Manual page 682

System DMA
58 Direct Memory Access (DMA) Support
Time-out error: An access error occurred in the transfer to the source or
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the destination, enabled with bit TOUT_IE in register DMA_CICR. The
countdown values are configured at the source and destination ports. No
countdown value can be specified in the system DMA.
Note:
Configure the interrupt(s) to be generated for each generic LCh in the chan-
nel interrupt control register (DMA_CICR). The LCh-D supports only two
kinds of interrupts. See Table 77, DMA LCD Control (DMA_LCD_CTRL) for
more information.
Each DMA logical channel can generate an interrupt to the MPU to reflect the
transfer status. Each system DMA logical channel has a dedicated interrupt
line to the MPU. All DMA interrupts are level sensitive interrupts; that is, an
interrupt line is held active-low until the MPU reads the associated logical
channel status register.
No new interrupts can be generated until the status register is read and thereby
cleared. For each logical channel, all the interrupt sources are connected
together to generate one interrupt. When an interrupt is issued by a logical
channel, its status register, DMA_CSR, is set to record the interrupt cause if
its associated DMA_CICR enable bit is set. The MPU interrupt service routine
(ISR) can read this channel status register to find the sources of the interrupt.
The status bits are automatically cleared after they are read by MPU.
The interrupt enable bits are used to choose the events that trigger the DMA
channel to send an interrupt to the processor. There are two classes of events:
Error event: errors during the transfer. These are time-out and request
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collision.
Status event: DMA transfer status during DMA channel transfers. These
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are start of last frame, half of frame, end of frame, and end of block.
When an error event occurs and the corresponding interrupt enable bit is
enabled, the following happens:
The status register bit is activated.
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An interrupt is generated.
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The logical channel is disabled.
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The physical channel is released.
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If there is an error but error interrupt is not enabled, no event is generated, the
status register bit is not set, and no interrupt is generated. However, the LCh
is disabled.
SPRU755B