Texas Instruments OMAP5912 Reference Manual page 162

Traffic Controller
Table 27. EMIFS Abort Time-Out Register (EMIFS_ATOR)
Bit Field
31:9 Reserved
8 TIMEOUT_EN
7:0 TIMEOUT
Table 28. Advanced EMIFS Chip-Select Configuration Registers
(EMIFS_ACS0, EMIFS_ACS1,...,EMIFS_ACS3)
Base Address = 0xFFFE CC00, Offset = 0x50, 0x54, 0x58, 0x5C
Bit Field
31:10 Reserved
9 BTMODE
8 ADVHOLD
7:4 OEHOLD
3:0 OESETUP
3.7 EMIFF Registers
104 OMAP3.2 Subsystem
Base Address = 0xFFFE CC00, Offset = 0x4C
Description
Reserved. To ensure software compatibility, reserved
bit should be write to 0 and read value should be
considered undefined.
Enable the time-out timer.
0: Timer is disable
1: Timer is enabled
Time out counter value in REF_CLK clock cycles.
Description
Reserved. To ensure software compatibility, reserved bit
should be write to 0 and read value should be considered
undefined.
Enables extended BTWST usage
0: Bus turn around control and RD to RD/WR same CS
pulse width high control
1: Bus turn around control and RD/WR to RD/WR same CS
pulse width high control
Controls the ADV pulse width low
Controls the number of cycles from OE high to CS high
Controls the number of cycles inserted from CS low to OE
low. When the MAD reset value is 1, the reset value of
OESETUP is 0x2 (See section 3.2.18 for MAD reset).
Table 29 lists the 32-bit EMIFF registers. Table 30 through Table 53 describe
the register bits.
R/W Reset
R/W 0x0000000
R/W 1
R/W 0xFF
R/W Reset
R/W 0x000000
R/W 0
R/W 0
R/W 0x0
R/W 0x0 or 0x2
SPRU749A