Texas Instruments OMAP5912 Reference Manual page 413

OMAP5912 Clock Architecture
5.14.3 CAM_CLK_OUT
5.14.4 SYS_CLK_OUT
58 Clocks
J
Set the SOFT_SDW_REQ bit to 1 in the ULPD SOFT_REQ_REG
register.
Consequently, the system clock is available on BCLK. Use SOFT_SDW_REQ
to disable or reenable BCLK (regardless of the BCLKREQ pin). When the
system clock is output on BCLK, the software can also use the ULPD
CLOCK_CTRL_REG.SDW_MCLK_INV to select the inactive level of BCLK.
For a divided 48-MHz clock on BCLK with a software request, the following
software procedure must be used. In the ULPD SDW_CLK_CTRL_DIV_SEL
register:
J
Set SDW_RATIO_SEL to the desired ratio.
J
Set the SDW_SYSCLK_PLLCLK_SEL bit to 0.
J
Set the SDW_ULPD_PLL_CLK_REQ to 1.
Consequently, the 48MHz clock divided by the programmed ratio will be
available on BCLK. Use SDW_ULPD_PLL_CLK_REQ to disable or re-enable
BCLK clock. By setting SDW_RATIO_SEL to 00000, 48MHz is made available
on BCLK.
Ball Y15 can also be configured to provide an external clock to a camera
sensor (CAM_CLK_OUT function, in multiplexing mode 6). The frequency of
this external clock is the system clock frequency divided by a programmable
ratio. It can only be enabled by software with the following procedure:
J
Set the CAM_CLK_DIV field to the appropriate dividing ratio in the
ULPD CAM_CLK_CTRL register.
J
Set the CAM_CLOCK_ENABLE
CAM_CLK_CTRL reigster.
Note:
CAM_CLK_OUT must not be confused with the CAM.EXCLK function:
CAM.EXCLK is the output pixel clock of the camera module;
CAM_CLK_OUT is merely the system clock divided. These two clocks have
different sources, and they are enabled differently
Ball B15 can be configured to function as SYS_CLK_OUT (in multiplexing
mode 1). The system clock can be enabled on this ball either by a hardware
or a software request.
SYS_CLK_OUT uses the same hardware request as MCLK (MCLKREQ). The
pin multiplexing should be setup so that ball R10 acts as MCLKREQ and ball
bit to 1 in the
SPRU751A
ULPD