Texas Instruments OMAP5912 Reference Manual page 1048

Table 36. Timer Status Register (TISR)
Base Address = 0xFFFB 1400 (n * 0x800, MPU), E101 1400 (n * 0x800, DSP); n = 0...7, Offset = 0x18
Bit Name
31:3 RESERVED
2 TCAR_IT_FLAG
1 OVF_IT_FLAG
0 MAT_IT_FLAG
SPRU759B
(LSB), 0x1A (MSB)
Function
0: No capture interrupt request
1: Capture interrupt request
0: No overflow interrupt request
1: Overflow interrupt pending
0: No compare interrupt request
1: Compare interrupt pending
The timer status register is used to determine which of the timer events
requested an interrupt. Bit 0 corresponds to the compare result of TCRR and
TMAR, and is set when the compare register matches the counter value. Bit
1 corresponds to the TCRR overflow; and bit 2 indicates that an external pulse
transition of the correct polarity is detected on the external event capture pin.
If the value is 1, then that timer event is requesting the interrupt. If the user
wants to reset the status bit, then a 1 must be written to the appropriate bit.
Writing a 1 to the bit TCAR_IT_FLAG resets the edge detection logic.
However, the user cannot generate an interrupt by writing a 1 to the timer
status register bits. If the user writes a 0 to a bit in the timer status register bits,
the value remains unchanged.
Dual-Mode Timer
R/W Reset
R 0x000 0000
R/W 0
R/W 0
R/W 0
Timers 45