Texas Instruments OMAP5912 Reference Manual page 1087

SPI Master/Slave
Table 6. Interrupt Status Register Bit Description (SPI_ISR—0x018)
Bit Name
31:5 Reserved
4 WAKEUP
3 TX_UNDERFLOW
2 RX_OVERFLOW
1 WE
0 RE
Table 7. Interrupt Enable Register Bit Description (SPI_IER—0x01C)
Bit Name
31:5 Reserved
4 MSK4
3 MSK3
2 MSK2
1 MSK1
0 MSK0
22 Serial Interfaces
Base Address = 0xFFFB 0C00, Offset = 0x18
Function
A read access returns 0.
Wake-up: Active high.
Transmit underflow: Active high.
Receive overflow: Active high.
Write end: Active high.
Serialization complete.
Read end: Active high.
Receive register updated.
The interrupt status register is used to qualify the interrupt. Writing a 1 to the
corresponding status bit releases the interrupt. Writing a 0 has no effect.
Base Address = 0xFFFB 0C00, Offset = 0x1C
Function
A read access returns 0.
Enable interrupt when wake up
0: Interrupt disabled.
1: Interrupt active.
Enable interrupt when TX underflow
0: Interrupt disabled.
1: Interrupt active.
Enable interrupt when RX overflow
0: Interrupt disabled.
1: Interrupt active.
Enable interrupt for write cycle
0: Interrupt disabled.
1: Interrupt active.
Enable interrupt for read cycle
0: Interrupt disabled.
1: Interrupt active.
Access Reset
R 0x0000000
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
Access Reset
R 0x0000000
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
SPRU760B