Bus Allocation - Texas Instruments OMAP5912 Reference Manual

Layer 4 Interconnect
2.3 Dynamic Switch
Figure 3. Dynamic Switch for OCP Peripheral
Synchronization with
dynamic switch clock
MPU
TIPB bridge
DSP
TIPB bridge
Note: Default value: To simplify the TIPB router implementation and reduce the toggling on buses, a default value is returned to
the host, which does not access the peripheral.
2.4 Functional Description
2.4.1

Bus Allocation

MPU/DSP TIPB Bridge to Peripherals
24 Peripheral Interconnects
allocation
Synchronization
with MPU strobe
Synchronization
with DSP strobe
The peripheral TIPB buses are shared between the MPU TIPB bridge and the
DSP TIPB bridge. Both bridges can access the same peripheral. Therefore,
a bus allocation module is required to decide which one can access to the
peripheral bus in case of conflict. This arbitration occurs after a
synchronization of the DSP enable signal with the dynamic switch clock
(ARMPER_CLK).
If no more than one of the two masters requests the bus, the bus is allocated
to the requesting master. Otherwise, the MPU TIPB bridge takes control of the
bus. DSP TIPB bridge accesses the peripheral after the data has been
returned to the MPU TIPB bridge. During the transfer, the access size can be
either 16-bit for the DSP or 8-, 16-, or 32-bit for the MPU.
Bus
module
TIPB to
OCP
interface
*Default
values
OCP to
OCP
TIPB
peripheral
interface
SPRU758A