Texas Instruments OMAP5912 Reference Manual page 982

Table 6. Static Switch Configuration Registers Offset Addresses (Continued)
Register Name
NFCtrl_SSW_DSP_CONF
MMCSD2_SSW_MPU_CONF
MMCSD2_SSW_DSP_CONF
Table 7. Peripheral MPU Static Switch Configuration Register (xxx_SSW
Bit Name
31:2 −
1 DSP_SWITCH
0 MPU_SWITCH
Table 8. Peripheral DSP Static Switch Configuration Register (xxx
Bit Name
15:2 −
1 DSP_SWITCH
0 MPU_SWITCH
SPRU758A
For each static-shared peripheral, two registers are defined (Table 7 and
Table 8): one is dedicated to MPU accesses, and the other to DSP accesses.
Base Address = FFFB C800, Offset Address = see Table 6
Description
Reserved
0: No DSP TIPB bridge access required
1: DSP TIPB bridge access required
0: No MPU TIPB bridge access required
1: MPU TIPB bridge access required
This register is only accessible through the MPU shared TIPB bridge.
It is used to perform MPU access on the peripheral.
Base Address = FFFB C800, Offset Address = see Table 6
Description
Reserved
0: No DSP TIPB bridge access required
1: DSP TIPB bridge access required
0: No MPU TIPB bridge access required
1: MPU TIPB bridge access required
This register is accessible only through the DSP shared TIPB bridge.
# Bits Offset
16
16/32 0x160
16
Peripheral Interconnects
Layer 4 Interconnect
Bus
DSP
MPU
DSP
MPU CONF
_ _
Access Reset
R 0x00000000
R 0
RW 1
SSW DSP CONF
_ _ _
Access Reset
R 0x00000000
RW 0
R 1
)
)
31