Texas Instruments OMAP5912 Reference Manual page 1119

SPI Master/Slave
54 Serial Interfaces
The ENAWAKEUP bit of the system configuration register (SPI_SCR) controls
this wake-up request.
When the system wakes up, the following actions are executed:
The idle request goes low (inactive).
-
The wake-up request is deasserted (in smart-idle mode only).
-
The WAKEUP status bit is set in the interrupt status register (SPI_ISR).
-
The idle acknowledge goes low (inactive).
-
An interrupt is generated if MSK4 is set in the interrupt enable register
-
(SPI_IER).
Once the SPI acknowledges the idle request, the functional and interface
clocks can be stopped one cycle later.
Some restrictions apply on the module functionality when a wake-up request
is generated (in Smart-Idle mode only). The following conditions must be met
to ensure the right behavior of the requested transaction:
The SPI must be in DMA mode: DMA_EN set in the set up register
-
(SPI_SET1 [5] = 1).
The requested transaction that wakes up the module must be a receive:
-
RD set and WR reset in the control register (SPI_CTRL [1:0] = 01).
The functional clock (CLK_M) must be active if the bit ENAWAKEUP
-
(SPI_SCR [2]) is set, in order to generate a wake-up request and to copy
the received data into the SPI_RX register. If the bit ENAWAKEUP is reset,
SPI does not work when receiving a read
The AUTOIDLE bit of the system configuration register (SPI_SCR [0]) can be
set in order to save power. This bit controls the internal OCP clock activity:
When this bit is cleared, the internal OCP clock is free-running.
-
When this bit is set, the internal OCP clock becomes inactive if the OCP
-
command is in IDLE
transaction.
state.
SPRU760B