Texas Instruments OMAP5912 Reference Manual page 232

MPU and MPUI Port
5.2.3 Memory Accesses in SAM
5.2.4 Peripheral Accesses in HOM
5.2.5 Peripheral Accesses in SAM
5.2.6 Posted Write Mode
174 OMAP3.2 Subsystem
When the MPUI port is in SAM_M mode, both the DSP and the MPU/system
DMA/OCP-I can access the SARAM, DARAM, and EMIF. In this mode, the
asynchronous host accesses from the MPU/system DMA/OCP-I are
resynchronized on the DSP clock internally in the MPUI port logic. In case of
conflict between the MPU/system DMA/OCP-I and the DSP accesses (i.e., the
MPU/system DMA/OCP-I and the DSP attempt to access same memory
block), the DSP has the priority and the MPU/system DMA/OCP-I access is
not acknowledged and is delayed by one or more cycles.
However, if an MPU/system DMA/OCP-I transfer has started before the DSP
request is received, the MPU/system DMA/OCP-I transfer is completed before
the DSP access is initiated.
In HOM_R mode, only the MPU/system DMA/OCP-I can access the DSP
shared peripherals and peripheral requests are completely asynchronous to
DSP clock. Therefore, peripheral accesses can be performed without any
resynchronization, allowing for faster communication between the
MPU/system DMA/OCP-I and the peripherals. In this mode, the MPUI port is
a simple bridge between the MPU/system DMA/OCP-I and the DSP TIPB
bridge for the address, data, and control signals.
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Any DSP access to the shared peripherals generates a bus error from the
DSP TIPB bridge.
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An MPUI access to a DSP private peripheral causes a time-out error.
When the MPUI port is in SAM_R mode, both the DSP and the MPU/system
DMA/OCP-I can access the peripherals. In this mode, the asynchronous host
accesses from the MPU/system DMA/OCP-I are resynchronized internally in
the MPUI port logic. In case of conflict between the MPU/system DMA/OCP-I
and the DSP accesses (i.e. the MPU/system DMA/OCP-I and the DSP attempt
to access the same peripheral at the same time), the DSP has the priority and
the MPU/system DMA/OCP-I waits one or more cycles.
However, if an MPU/system DMA/OCP-I transfer has begun before a DSP
request is received, the MPU/system DMA/OCP-I transfer is completed before
the DSP access is initiated. The goal is to ensure a smooth transition, with no
spurious reads or writes and no lost reads or writes.
System performances can be enhanced by enabling the posted write mode
when the MPUI port RAM and DSP TIPB are in SAM. The MPU/system
SPRU749A