Bmode Switching; Missing Input Clock; Omap3.2 Dpll - Texas Instruments OMAP5912 Reference Manual

OMAP3.2 DPLL

BMode Switching

Missing Input Clock

3 OMAP3.2 DPLL
20 Clocks
The fast lockup scheme changes the APLL operation mode. The selection bits
must not be changed during normal operation.
If the above condition is not met, be aware that:
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Digital state machines have been designed in such a way to avoid any
deadlock condition, but any switching different from the above can lead to
unpredictable long transients that differ considerably from case to case.
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The lock signal behavior is not deterministic during mode switching. It
goes back to a lower state or it stays high, depending on conditions.
Because of the important time-consistent feature of this signal, it is
reasonable to expect the APLL to react faster. The lock signal goes low
only in major failure conditions, that is, absence of an input clock for a long
period of time or a bad frequency range.
A missing input clock is a major concern. It is associated with a lock going low
after several 100 µs, depending on mode and condition.
It also causes the output frequency on CLKOUT to decrease quickly because
the APLL tries to lock on a 0 frequency signal. However, this is limited to the
APLL lock-in range. An unstable frequency can be expected in association
with potential beats.
When the input clock is reactivated for a long period of time, the APLL returns
to lock condition afterwards. However, this may take longer than usual, up to
five times more than the specified lock-in time. In that event, the fast lockup
sequence can be used.
One clock source can be switched to another in the same mode without using
PWRDN. Clock-gating cells must handle this switching to prevent glitches and
clock uncertainty. A jitter outside the specification affects this clock switching,
especially if a large guard is inserted between the clock source activations with
many missing pulses and a large phase jump.
The two most important uses of phase-locked loops are as synthesizers and
synchronizers. Synthesizers generate a variable-frequency clock from a
fixed-frequency reference clock. The output frequency of the PLL is an integer
multiple or a fractional multiple (M/N) of the input reference. Synchronizers
SPRU751A