Texas Instruments OMAP5912 Reference Manual page 908

Multimedia processor device overview and architecture

Hide thumbs Also See for OMAP5912:

Table of Contents

Interrupt Overview

Interrupt Interconnect

DSP interrupt

handler level 2.1

DSP interrupt

handler level 2.0

peripherals :

3 DSP timers

DSP watchdog

DSP interrupt

Two DSP level 2 interrupt handlers connect directly to the DSP interrupt

interface and then to the DSP level 1 interrupt handler. One MPU level 2

interrupt handler connects in parallel to the MPU level 1 interrupt handler. For

more detail on the architecture and programming model of the level 2 interrupt

handler, see Section 2, Interrupt Controller.

There are four groups of shared peripherals. Most of the shared peripherals

connect to DSP/MPU level 2 interrupt handlers. Two exceptions are the GPIO1

and UART3, which connect to the MPU level 1 handler and the DSP level 1

Table 1 through Table 5 include the default priority and the required sensitivity

to be programmed by software per interrupt line for each interrupt handler (L1

and L2). When the sensitivity is not precise, it must be considered as edge. The

sensitivity depends on the peripheral type.

MPU interrupt

handler level 2

GPIOs wake up

CompactFlash

MPU interrupt

peripherals:

handler level 1

3 MPU timers

MPU watchdog

Chapters

Table of Contents