Texas Instruments OMAP5912 Reference Manual page 219

Table 80. DSP Clock Reset Status Register (DSP_SYSST)
Bit Name
15:14 RESERVED
13:11 CLOCK_SELECT
10:7 RESERVED
6 IDLE_ARM
5 POR
4 EXT_RST
SPRU749A
Base Address = 0xE100 8000 or 0x008000, Offset = 0x18
Function
Reading these bits gives undefined values. Writing to
them has no effect.
These read-only bits reflect the CLOCK_SELECT
pins and indicate the current clocking mode selection.
000: Fully synchronous
001: Reserved
010: Synchronous scalable.
011: Reserved
100: Reserved
101: Bypass
110: Mix mode #3, MPU synchronous to TC, DSP
MMU synchronous scalar to MPU and TC
111: Mix mode #4, DSP MMU synchronous to TC,
MPU synchronous scalar to DSP MMU and TC
Reserved bits
Indicates the MPU state
0: The MPU is active.
1: The MPU is in idle state.
Indicates (in conjunction with EXT_RST bit) whether
or not a power-on reset (cold start) has occurred.
Writing it to logic 0 clears this bit. This bit cannot be
written to logic 1 from the TIPB interface.
0: No power-on reset has been detected.
1: A power-on reset has occurred.
Indicates whether or not an external reset has been
asserted. Writing it to logic 0 clears this bit. This bit
cannot be written to logic 1 from the TIPB interface.
0: No external reset detected.
1: An external reset has been asserted.
Clock Generation and Reset Management
R/W
R/W
OMAP3.2 Subsystem
Reset
00
R 000
R 0000
R 0
R/C 1
R/C 1
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