Texas Instruments OMAP5912 Reference Manual page 355

Index
DSP core 17
DSP CPU 18
EMIF 57
memory 22
MMU 58
MPUI 54
system operating details 83
TIPB bridge 47
DSP subsystem boot mode 84
DSP subsystem peripherals 17
DSP system operation 83
DSP/MPU shared peripherals 84
private peripherals 83
public peripherals 84
subsystem boot mode 84
DSP TIPB bridge 47
control mode register 50
idle registers 52
DSP TIPB control mode register 50
DSP TIPB idle registers 52
DSP/MPU shared peripherals 84
E
Enable and disable instruction cache 33
92 OMAP5912
H
HOM/SAM 56
I
Instruction cache freeze mode 34
Instruction cache operation 27
O
On−chip memory 19
P
Programming, architecture, maximum
performance 22
R
Ramset functional configuration 33
S
ST3−HOM_P 56
ST3−HOM_R 56
SPRU750A