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Table 17. Electrical Specification of the Input/Output
Parameter
Parameter
VIL
Low-level input voltage:
Fixed input levels
VDD-related input levels
VIH
High-level input voltage:
Fixed input levels
VDD-related input levels
Low-level output voltage:
VDD>2V
VOL1
At 3mA sink current
VOL2
At 6mA sink current
VDD<2V
VOL3
At 3mA sink current
2.5.3
Data Validity
Figure 18.
Bit Transfer on the I
SDA
SCL
SPRU760B
Standard Mode
Min
−0.5
−0.5
3.0
0.7VDD
0
n/a
n/a
The data on the SDA line must be stable during the high period of the clock.
The high and low states of the data line can change only when the clock signal
on the SCL line is low.
2
C Bus
Data line
stable,
data valid
Devices
Max
Min
1.5
n/a
0.3VDD
−0.5
VDDmax+0.5
n/a
VDDmax+0.5
0.7VDD
0.4
0
n/a
0
n/a
0
Change
of data
allowed
I2C Multimaster Peripheral
Fast-Mode
Devices
Unit
Unit
Max
n/a
V
0.3VDD
n/a
V
VDDmax+0.5
0.4
V
0.6
0.2VDD
Serial Interfaces
59
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