Texas Instruments OMAP5912 Reference Manual page 828

Multimedia processor device overview and architecture

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Memory Interfaces for the EMIFS

Command Operations

Read 1 (lower half-page or Area A)

Read 1 (upper half-page or Area B)

Read 2 (spare or Area C)

Page program

Multiple-page program

Copy-back program

Multiple copy-back program

Multiplane block erase

Read multiplane status

Memory Interfaces

Associated with this 8-bit bus are qualifiers: CLE (command latch enable)

which characterizes that the data on the bus is a command, and ALE (address

latch enable), which characterizes that the value on the bus is an address.

When CLE is low and ALE is low, the value on the bus is a data. The

combination CLE high and ALE high is not permitted. Reading data requires

a negative pulse on signal RE_. Writing command/address/data requires a

negative pulse on signal WE_.

For program operation, data is latched into the NFMC on the rising edge of

WE_. For read operation, data is latched on the falling edge of RE_. The NFMC

signal Ready/Busy_ (R/B_) indicates the status of the ongoing operation.

When low, R/B_ indicates that a program read or erase is in process and

returns to high state upon completion. When returning high, the NFC also

asserts an interrupt so that the local host can be aware that the ongoing

operation is completed.

The core memory check page reference inside the core is organized by a page

of 512 bytes and a spare area of 16 bytes for the most recent NFMC, as shown

in Figure 18, Single Page Program DMA in Postwrite Mode.

The 528-byte page is itself divided into two main areas, A (from 0 to 255) and

B (from 256 to 511), and a C or spare area (from 512 to 527). To access area

Second Cycle

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