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Texas Instruments TMS320DM646x User Manual

Texas Instruments TMS320DM646x User Manual

Texas instruments ethernet media access controller (emac)/ management data input/output (mdio) module user's guide
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TMS320DM646x DMSoC
Ethernet Media Access Controller (EMAC)/
Management Data Input/Output (MDIO)
Module
User's Guide
Literature Number: SPRUEQ6
December 2007

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Summary of Contents for Texas Instruments TMS320DM646x

  • Page 1 TMS320DM646x DMSoC Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO) Module User's Guide Literature Number: SPRUEQ6 December 2007...
  • Page 2 SPRUEQ6 – December 2007 Submit Documentation Feedback...

  • Page 3: Table Of Contents

    Preface Introduction Purpose of the Peripheral Features Functional Block Diagram Industry Standard(s) Compliance Statement Architecture Clock Control Memory Map Signal Descriptions Ethernet Protocol Overview Programming Interface EMAC Control Module MDIO Module EMAC Module Media Independent Interface (MII) 2.10 Packet Receive Operation 2.11 Packet Transmit Operation 2.12...
  • Page 4 PHY Acknowledge Status Register (ALIVE) PHY Link Status Register (LINK) MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) 4.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)
  • Page 5 5.36 MAC Source Address High Bytes Register (MACSRCADDRHI) 5.37 MAC Hash Address Register 1 (MACHASH1) 5.38 MAC Hash Address Register 2 (MACHASH2) 5.39 Back Off Test Register (BOFFTEST) 5.40 Transmit Pacing Algorithm Test Register (TPACETEST) 5.41 Receive Pause Timer Register (RXPAUSE) 5.42 Transmit Pause Timer Register (TXPAUSE) 5.43...

  • Page 6: List Of Figures

    EMAC and MDIO Block Diagram Ethernet Configuration—MII Connections Ethernet Configuration—GMII Connections Ethernet Frame Format Basic Descriptor Format Typical Descriptor Linked List Transmit Buffer Descriptor Format Receive Buffer Descriptor Format EMAC Control Module Block Diagram MDIO Module Block Diagram EMAC Module Block Diagram EMAC Control Module Interrupt Logic Diagram EMAC Control Module Identification and Version Register (CMIDVER) EMAC Control Module Software Reset Register (CMSOFTRESET)
  • Page 7 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Receive Interrupt Mask Set Register (RXINTMASKSET) Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) MAC Interrupt Mask Set Register (MACINTMASKSET) MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Receive Unicast Enable Set Register (RXUNICASTSET)
  • Page 8 EMAC and MDIO Signals for MII Interface EMAC and MDIO Signals for GMII Interface Ethernet Frame Description Basic Descriptor Description EMAC Control Module Interrupts Receive Frame Treatment Summary Middle of Frame Overrun Treatment Emulation Control EMAC Control Module Registers EMAC Control Module Identification and Version Register (CMIDVER) Field Descriptions EMAC Control Module Software Reset Register (CMSOFTRESET) Field Descriptions EMAC Control Module Emulation Control Register (CMEMCONTROL) Field Descriptions EMAC Control Module Interrupt Control Register (CMINTCTRL) Field Descriptions...
  • Page 9 Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions MAC Input Vector Register (MACINVECTOR) Field Descriptions MAC End Of Interrupt Vector Register (MACEOIVECTOR) Field Descriptions Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions...

  • Page 10: Preface

    (PHY) device Management Data Input/Output (MDIO) module integrated in the TMS320DM646x Digital Media System-on-Chip. Included are the features of the EMAC and MDIO modules, a discussion of their architecture and operation, how these modules connect to the outside world, and the registers description for each module.
  • Page 11 (DSP) megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache. SPRUEQ6 – December 2007 Submit Documentation Feedback Related Documentation From Texas Instruments Read This First...

  • Page 12: Introduction

    Ethernet Media Access Controller (EMAC)/Management Introduction This document provides a functional description of the Ethernet Media Access Controller (EMAC) and physical layer (PHY) device Management Data Input/Output (MDIO) module integrated in theTMS320DM646x Digital Media System-on-Chip. Included are the features of the EMAC and MDIO modules, a discussion of their architecture and operation, how these modules connect to the outside world, and a description of the registers for each module.

  • Page 13: Functional Block Diagram

    www.ti.com No-chain mode truncates frame to first buffer for network analysis applications. Emulation support. Loopback mode. Functional Block Diagram Figure 1 shows the three main functional modules of the EMAC/MDIO peripheral: EMAC control module EMAC module MDIO module The EMAC control module is the main interface between the device core processor and the EMAC module and MDIO module.

  • Page 14: Industry Standard(S) Compliance Statement

    Architecture The EMAC and MDIO interrupts are combined within the control module, so only the control module interrupt needs to be monitored by the application software or device driver. The EMAC control module combines the EMAC and MDIO interrupts and generates 4 separate interrupts to the ARM through the ARM interrupt controller.

  • Page 15: Memory Map

    www.ti.com Memory Map The EMAC peripheral includes internal memory that is used to hold information about the Ethernet packets received and transmitted. This internal RAM is 2K read from the EMAC internal memory by either the EMAC or the CPU. It is used to store buffer descriptors that are 4-words (16-bytes) deep.

  • Page 16: Emac And Mdio Signals For Mii Interface

    Architecture Table 1. EMAC and MDIO Signals for MII Interface Signal Type Description MTCLK Transmit clock (MTCLK). The transmit clock is a continuous clock that provides the timing reference for transmit operations. The MTXD and MTXEN signals are tied to this clock. The clock is generated by the PHY and is 2.5 MHZ at 10 Mbps operation and 25 MHZ at 100 Mbps operation.

  • Page 17: Ethernet Configuration-Gmii Connections

    www.ti.com 2.3.2 Gigabit Media Independent Interface (GMII) Connections Figure 3 shows a device with integrated EMAC and MDIO interfaced via a GMII connection. This interface is available in 10 Mbps, 100 Mbps, and 1000 Mbps modes. The GMII interface supports 10/100/1000 Mbps modes. Only full-duplex mode is available in 1000 Mbps mode.
  • Page 18 Architecture Table 2. EMAC and MDIO Signals for GMII Interface (continued) Signal Type Description MCRS Carrier sense (MCRS). The MCRS pin is asserted by the PHY when the network is not idle in either transmit or receive. The pin is de-asserted when both transmit and receive are idle. This signal is not necessarily synchronous to MTCLK nor MRCLK.

  • Page 19: Ethernet Protocol Overview

    www.ti.com Ethernet Protocol Overview Ethernet provides an unreliable, connection-less service to a networking application. A brief overview of the Ethernet protocol is given in the following subsections. For in-depth information on the Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method, which is the Ethernet’s multiple access protocol, see the IEEE 802.3 standard document.

  • Page 20: Programming Interface

    Architecture 2.4.2 Ethernet’s Multiple Access Protocol Nodes in an Ethernet Local Area Network are interconnected by a broadcast channel, as a result, when an EMAC port transmits a frame, all the adapters on the local network receive the frame. Carrier Sense Multiple Access with Collision Detection (CSMA/CD) algorithms are used when the EMAC operates in half-duplex mode.

  • Page 21: Typical Descriptor Linked List

    www.ti.com Word Offset Field Next Descriptor Pointer Buffer Pointer Buffer Offset Buffer Length Flags Packet Length SPRUEQ6 – December 2007 Submit Documentation Feedback Table 4. Basic Descriptor Description Field Description The next descriptor pointer is used to create a single linked list of descriptors. Each descriptor describes a packet or a packet fragment.
  • Page 22 Architecture 2.5.2 Transmit and Receive Descriptor Queues The EMAC module processes descriptors in linked list chains as discussed in controlled by the EMAC are maintained by the application software through the use of the head descriptor pointer registers (HDP). Since the EMAC supports eight channels for both transmit and receive, there are eight head descriptor pointer registers for both.
  • Page 23 www.ti.com 2.5.3 Transmit and Receive EMAC Interrupts The EMAC processes descriptors in linked list chains as discussed in queue mechanism discussed in The EMAC synchronizes descriptor list processing through the use of interrupts to the software application. The interrupts are controlled by the application using the interrupt masks, global interrupt enable, and the completion pointer register (CP).

  • Page 24: Transmit Buffer Descriptor Format

    Architecture 2.5.4 Transmit Buffer Descriptor Format A transmit (TX) buffer descriptor 32-bit boundary that describes a packet or a packet fragment. descriptor described by a C structure. Word 0 Word 1 Word 2 Buffer Offset Word 3 OWNER TDOWNCMPLT Example 1. Transmit Buffer Descriptor in C Structure Format // EMAC Descriptor // The following is the format of a single buffer descriptor...
  • Page 25 www.ti.com 2.5.4.1 Next Descriptor Pointer The next descriptor pointer points to the 32-bit word aligned memory address of the next buffer descriptor in the transmit queue. This pointer is used to create a linked list of buffer descriptors. If the value of this pointer is zero, then the current buffer is the last buffer in the queue.
  • Page 26 Architecture 2.5.4.7 End of Packet (EOP) Flag When set, this flag indicates that the descriptor points to a packet buffer that is last for a given packet. In the case of a single fragment packet, both the start of packet (SOP) and EOP flags are set. Otherwise, the descriptor pointing to the last packet buffer for the packet sets the EOP flag.

  • Page 27: Receive Buffer Descriptor Format

    www.ti.com 2.5.5 Receive Buffer Descriptor Format A receive (RX) buffer descriptor 32-bit boundary that describes a packet or a packet fragment. descriptor described by a C structure. 2.5.5.1 Next Descriptor Pointer This pointer points to the 32–bit word aligned memory address of the next buffer descriptor in the receive queue.
  • Page 28 Architecture Example 2. Receive Buffer Descriptor in C Structure Format // EMAC Descriptor // The following is the format of a single buffer descriptor // on the EMAC. typedef struct _EMAC_Desc { struct _EMAC_Desc *pNext; Uint8 *pBuffer; Uint32 BufOffLen; Uint32 PktFlgLen;...
  • Page 29 www.ti.com 2.5.5.4 Buffer Length This 16-bit field is used for two purposes: Before the descriptor is first placed on the receive queue by the application software, the buffer length field is first initialized by the software to have the physical size of the empty data buffer pointed to by the buffer pointer field.
  • Page 30 Architecture 2.5.5.10 Teardown Complete (TDOWNCMPLT) Flag This flag is used when a receive queue is being torn down, or aborted, instead of being filled with received data. This would happen under device driver reset or shutdown conditions. The EMAC sets this bit in the descriptor of the first free buffer when the tear down occurs.

  • Page 31: Emac Control Module

    www.ti.com 2.5.5.21 No Match (NOMATCH) Flag This flag is set by the EMAC in the SOP buffer descriptor, if the received packet did not pass any of the EMAC’s address match criteria and was not discarded because the RXCAFEN bit was set in the RXMBPENABLE.

  • Page 32: Emac Control Module Interrupts

    Architecture 2.6.3 Interrupt Control The EMAC control module combines multiple interrupt conditions generated by the EMAC and MDIO modules into four separate interrupt signals interrupt controller. The four separate sources of interrupt can be individually enabled for each channel by the CMRXTHRESHINTEN, CMRXINTEN, CMTXINTEN, and CMMISCINTEN registers.
  • Page 33 www.ti.com 2.6.3.3 Receive Threshold Pulse Interrupt The EMAC control module receives the eight individual receive threshold interrupts originating from the EMAC module, one for each of the eight channels, and combines them into a single receive threshold pulse interrupt to the CPU. This receive threshold pulse interrupt is not paced. The eight individual receive threshold pending interrupt(s) are selected at the EMAC control module level, by setting one or more bits in the EMAC control module receive threshold interrupt enable register (CMRXTHRESHINTEN).

  • Page 34: Mdio Module

    Architecture If the rate of transmit pulse interrupt inputs is much less than the target transmit pulse interrupt rate specified in CMTXINTMAX, then the interrupts are not blocked to the CPU. If the transmit pulse interrupt rate is greater than the specified target rate in CMTXINTMAX, the interrupt is paced at the rate specified in this register, which should be written with a value between 2 and 63 inclusive, indicating the target number of interrupts per 1 ms going to the CPU.
  • Page 35 www.ti.com 2.7.1.2 Global PHY Detection and Link State Monitoring The MDIO module continuously polls all 32 MDIO addresses in order to enumerate the PHY devices in the system. The module tracks whether or not a PHY on a particular address has responded, and whether or not the PHY currently has a link.
  • Page 36 Architecture A round-robin arbitration scheme is used to schedule transactions that may be queued using both USERACCESS0 and USERACCESS1. The application software must check the status of the GO bit in USERACCESSn before initiating a new transaction, to ensure that the previous transaction has completed.
  • Page 37 www.ti.com 2.7.2.4 Example of MDIO Register Access Code The MDIO module uses the MDIO user access register (USERACCESSn) to access the PHY control registers. Software functions that implement the access process may simply be the following four macros: PHYREG_read( regadr, phyadr ) PHYREG_write( regadr, phyadr, data ) PHYREG_wait( ) PHYREG_waitResults( results )

  • Page 38: Emac Module

    Architecture EMAC Module This section discusses the architecture and basic function of the EMAC module. 2.8.1 EMAC Module Components The EMAC module (Figure 11) interfaces to the outside world through the Media Independent Interface (MII) and interfaces to the system core through the EMAC control module. The EMAC consists of the following logical components: The receive path includes: receive DMA engine, receive FIFO, and MAC receiver The transmit path includes: transmit DMA engine, transmit FIFO, and MAC transmitter...
  • Page 39 www.ti.com 2.8.1.3 MAC Receiver The MAC receiver detects and processes incoming network frames, de-frames them, and puts them into the receive FIFO. The MAC receiver also detects errors and passes statistics to the statistics RAM. 2.8.1.4 Receive Address This sub-module performs address matching and address filtering based on the incoming packet’s destination address.
  • Page 40 Architecture 2.8.2 EMAC Module Operational Overview After reset, initialization, and configuration, the application software running on the host may initiate transmit operations. Transmit operations are initiated by host writes to the appropriate transmit channel head descriptor pointer contained in the state RAM block. The transmit DMA controller then fetches the first packet in the packet chain from memory.

  • Page 41: Media Independent Interface (Mii)

    www.ti.com Media Independent Interface (MII) The following sections discuss the operation of the Media Independent Interface (MII) in 10 Mbps and 100 Mbps mode. An IEEE 802.3 compliant Ethernet MAC controls the interface. 2.9.1 Data Reception 2.9.1.1 Receive Control Data received from the PHY is interpreted and output to the EMAC receive FIFO. Interpretation involves detection and removal of the preamble and start-of-frame delimiter, extraction of the address and frame length, data handling, error checking and reporting, cyclic redundancy checking (CRC), and statistics control signal generation.
  • Page 42 Architecture 2.9.1.3.1 Collision-Based Receive Buffer Flow Control Collision-based receive buffer flow control provides a means of preventing frame reception when the EMAC is operating in half-duplex mode (the FULLDUPLEX bit is cleared in MACCONTROL). When receive flow control is enabled and triggered, the EMAC generates collisions for received frames. The jam sequence transmitted is the 12-byte sequence C3.C3.C3.C3.C3.C3.C3.C3.C3.C3.C3.C3h.
  • Page 43 www.ti.com 2.9.2 Data Transmission The EMAC passes data to the PHY from the transmit FIFO (when enabled). Data is synchronized to the transmit clock rate. Transmission begins when there are TXCELLTHRESH cells of 64 bytes each, or a complete packet, in the FIFO. 2.9.2.1 Transmit Control A jam sequence is output if a collision is detected on a transmit packet.
  • Page 44 Architecture 2.9.2.6 Transmit Flow Control Incoming pause frames are acted upon, when enabled, to prevent the EMAC from transmitting any further frames. Incoming pause frames are only acted upon when the FULLDUPLEX and TXFLOWEN bits in the MAC control register (MACCONTROL) are set. Pause frames are not acted upon in half-duplex mode. Pause frame action is taken if enabled, but normally the frame is filtered and not transferred to memory.

  • Page 45: 2.10 Packet Receive Operation

    www.ti.com 2.10 Packet Receive Operation 2.10.1 Receive DMA Host Configuration To configure the receive DMA for operation the host must: Initialize the receive addresses. Initialize the receive channel n DMA head descriptor pointer registers (RXnHDP) to 0. Write the MAC address hash n registers (MACHASH1 and MACHASH2), if hash matching multicast addressing is desired.
  • Page 46 Architecture 2.10.3 Receive Address Matching The receive address block can store up to 32 addresses to be filtered or matched. Before enabling packet reception, all the address RAM locations should be initialized, including locations to be unused. The system software is responsible for adding and removing addresses from the RAM. A MAC address location in RAM is 53 bits wide and consists of: 48 bits of the MAC address.
  • Page 47 www.ti.com to the appropriate receive channel n free buffer count registers (RXnFREEBUFFER). The EMAC decrements the appropriate channel’s free buffer value for each buffer used. When the host reclaims the frame buffers, the host should write the channel free buffer register with the number of reclaimed buffers (write to increment).

  • Page 48: Receive Frame Treatment Summary

    Architecture 2.10.8 Promiscuous Receive Mode When the promiscuous receive mode is enabled by setting the RXCAFEN bit in the receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE), nonaddress matching frames that would normally be filtered are transferred to the promiscuous channel. Address matching frames that would normally be filtered due to errors are transferred to the address match channel when the RXCAFEN and RXCEFEN bits in RXMBPENABLE are set.

  • Page 49: Middle Of Frame Overrun Treatment

    www.ti.com Table 6. Receive Frame Treatment Summary (continued) Address Match RXCAFEN 2.10.9 Receive Overrun The types of receive overrun are: FIFO start of frame overrun (FIFO_SOF) FIFO middle of frame overrun (FIFO_MOF) DMA start of frame overrun (DMA_SOF) DMA middle of frame overrun (DMA_MOF) The statistics counters used to track these types of receive overrun are: Receive start of frame overruns register (RXSOFOVERRUNS) Receive middle of frame overruns register (RXMOFOVERRUNS)

  • Page 50: 2.11 Packet Transmit Operation

    Architecture 2.11 Packet Transmit Operation The transmit DMA is an eight channel interface. Priority between the eight queues may be either fixed or round-robin as selected by the TXPTYPE bit in the MAC control register (MACCONTROL). If the priority type is fixed, then channel 7 has the highest priority and channel 0 has the lowest priority. Round-robin priority proceeds from channel 0 to channel 7.

  • Page 51: 2.13 Transfer Node Priority

    www.ti.com Receive overrun is prevented if the receive memory cell latency is less than the time required to transmit a 64-byte cell on the wire (0.512 ms in 1 Gbps mode, 5.12 ms in 100 Mbps mode, or 51.2ms in 10 Mbps mode).

  • Page 52: 2.15 Initialization

    The EMAC/MDIO is enabled through the Power and Sleep Controller (PSC) registers. For information on how to enable the EMAC peripheral from the PSC, see the TMS320DM646x DMSoC ARM Subsystem Reference Guide (SPRUEP9).
  • Page 53 www.ti.com Example 4. EMAC Control Module Initialization Code Uint32 tmpval ; /* Disable all the EMAC/MDIO interrupts in the control module */ EmacControlRegs->CONTROL.C_RX_EN EmacControlRegs->CONTROL.C_TX_EN EmacControlRegs->CONTROL.C_RX_THRESH_EN = 0; EmacControlRegs->CONTROL.C_MISC_EN /* Wait about 100 cycles */ for( I=0; i<5; I++ ) tmpval = ECTL_REGS->EWCTL ; #ifdef INTT_PACING /* Set the control related to pacing of TX and RX interrupts */ EmacControlRegs->INTR_COUNT->C_RX_IMAX = 0x4;...
  • Page 54 Architecture 2.15.3 MDIO Module Initialization The MDIO module is used to initially configure and monitor one or more external PHY devices. Other than initializing the software state machine (details on this state machine can be found in the IEEE 802.3 standard), all that needs to be done for the MDIO module is to enable the MDIO engine and to configure the clock divider.
  • Page 55 www.ti.com 2.15.4 EMAC Module Initialization The EMAC module is used to send and receive data packets over the network. This is done by maintaining up to eight transmit and receive descriptor queues. The EMAC module configuration must also be kept up-to-date based on PHY negotiation results returned from the MDIO module. Most of the work in developing an application or device driver for Ethernet is programming this module.

  • Page 56: 2.16 Interrupt Support

    Architecture 2.16 Interrupt Support 2.16.1 EMAC Module Interrupt Events and Requests The EMAC module generates the following interrupt events: RXTHRESHOLDPENDn: Receive threshold interrupt for receive channels 0 through 7 RXPENDn: Receive packet completion interrupt for receive channels 0 through 7 TXPENDn: Transmit packet completion interrupt for transmit channels 0 through 7 STATPEND: Statistics interrupt HOSTPEND: Host error interrupt...
  • Page 57 www.ti.com 2.16.1.2 Transmit Packet Completion Interrupts The transmit DMA engine has eight channels, with each channel having a corresponding interrupt (TXPENDn). The transmit interrupts are level interrupts that remain asserted until cleared by the CPU. Each of the eight transmit channel interrupts may be individually enabled by setting the corresponding bit in the transmit interrupt mask set register (TXINTMASKSET) to 1.
  • Page 58 Architecture The EMAC write to the completion pointer actually stores the value in the state RAM. The CPU written value does not actually change the register value. The host written value is compared to the register content (which was written by the EMAC) and if the two values are equal then the interrupt is removed; otherwise, the interrupt remains asserted.
  • Page 59 MACINVECTOR combines the status of the following 28 interrupt signals: TXPENDn, RXPENDn, RXTHRESHPENDn, STATPEND, HOSTPEND, LINKINT, and USERINT. For more details on the ARM interrupt controller (AINTC), see the TMS320DM646x DMSoC ARM Subsystem Reference Guide (SPRUEP9). SPRUEQ6 – December 2007...

  • Page 60: 2.17 Power Management

    When powering-up after a synchronized reset, all the EMAC submodules need to be reinitialized before any data transmission can happen. For more information on the use of the processor Power and Sleep Controller (PSC), see the TMS320DM646x DMSoC ARM Subsystem Reference Guide (SPRUEP9). 2.18 Emulation Considerations Note: For correct operation, the EMAC and EMAC control module must both be suspended.

  • Page 61: Emac Control Module Registers

    www.ti.com EMAC Control Module Registers Table 9 lists the memory-mapped registers for the EMAC control module. See the device-specific data manual for the memory address of these registers. Slave VBUS Address Acronym CMIDVER CMSOFTRESET CMEMCONTROL CMINTCTRL CMRXTHRESHINTEN CMRXINTEN CMTXINTEN CMMISCINTEN CMRXTHRESHINTSTAT CMRXINTSTAT CMTXINTSTAT...

  • Page 62: Emac Control Module Software Reset Register (Cmsoftreset)

    EMAC Control Module Registers EMAC Control Module Software Reset Register (CMSOFTRESET) The software reset register (CMSOFTRESET) is shown in Figure 14. EMAC Control Module Software Reset Register (CMSOFTRESET) LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 11.

  • Page 63: Emac Control Module Interrupt Control Register (Cmintctrl)

    www.ti.com EMAC Control Module Interrupt Control Register (CMINTCTRL) The interrupt control register (CMINTCTRL) is shown in Figure 16. EMAC Control Module Interrupt Control Register (CMINTCTRL) Reserved R/W-0 Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 13.

  • Page 64: Emac Control Module Receive Threshold Interrupt Enable Register (Cmrxthreshinten)

    EMAC Control Module Registers EMAC Control Module Receive Threshold Interrupt Enable Register (CMRXTHRESHINTEN) The receive threshold interrupt enable register (CMRXTHRESHINTEN) is shown in described in Table Figure 17. EMAC Control Module Receive Threshold Interrupt Enable Register Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 14.

  • Page 65: Emac Control Module Transmit Interrupt Enable Register (Cmtxinten)

    www.ti.com EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN) The transmit interrupt enable register (CMTXINTEN) is shown in Figure 19. EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN) Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 16.

  • Page 66: Emac Control Module Miscellaneous Interrupt Enable Register (Cmmiscinten)

    EMAC Control Module Registers EMAC Control Module Miscellaneous Interrupt Enable Register (CMMISCINTEN) The miscellaneous interrupt enable register (CMMISCINTEN) is shown in Table Figure 20. EMAC Control Module Miscellaneous Interrupt Enable Register (CMMISCINTEN) Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 17.

  • Page 67: Emac Control Module Receive Threshold Interrupt Status Register

    www.ti.com EMAC Control Module Receive Threshold Interrupt Status Register (CMRXTHRESHINTSTAT) The receive threshold interrupt status register (CMRXTHRESHINTSTAT) is shown in described in Table Figure 21. EMAC Control Module Receive Threshold Interrupt Status Register Reserved LEGEND: R = Read only; -n = value after reset Table 18.

  • Page 68: Emac Control Module Transmit Interrupt Status Register (Cmtxintstat)

    EMAC Control Module Registers 3.11 EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT) The transmit interrupt status register (CMTXINTSTAT) is shown in Figure 23. EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT) Reserved LEGEND: R = Read only; -n = value after reset Table 20.

  • Page 69: Emac Control Module Miscellaneous Interrupt Status Register (Ewmiscstat)

    www.ti.com 3.12 EMAC Control Module Miscellaneous Interrupt Status Register (EWMISCSTAT) The miscellaneous interrupt status register (EWMISCSTAT) is shown in Table Figure 24. EMAC Control Module Miscellaneous Interrupt Status Register (CMMISCINTSTAT) Reserved LEGEND: R = Read only; -n = value after reset Table 21.

  • Page 70: Emac Control Module Receive Interrupts Per Millisecond Register (Cmrxintmax)

    EMAC Control Module Registers 3.13 EMAC Control Module Receive Interrupts per Millisecond Register (CMRXINTMAX) The receive interrupts per millisecond register (CMRXINTMAX) is shown in Table Figure 25. EMAC Control Module Receive Interrupts per Millisecond Register (CMRXINTMAX) Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22.

  • Page 71: Mdio Registers

    www.ti.com MDIO Registers Table 24 lists the memory-mapped registers for the MDIO module. See the device-specific data manual for the memory address of these registers. Table 24. Management Data Input/Output (MDIO) Registers Offset Acronym VERSION CONTROL ALIVE LINK LINKINTRAW LINKINTMASKED USERINTRAW USERINTMASKED USERINTMASKSET...

  • Page 72: Mdio Control Register (Control)

    MDIO Registers MDIO Control Register (CONTROL) The MDIO control register (CONTROL) is shown in IDLE ENABLE Rsvd HIGHEST_USER_CHANNEL R/W-0 LEGEND: R/W = R = Read only; R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect; -n = value after reset Table 26.

  • Page 73: Phy Acknowledge Status Register (Alive)

    www.ti.com PHY Acknowledge Status Register (ALIVE) The PHY acknowledge status register (ALIVE) is shown in Figure 29. PHY Acknowledge Status Register (ALIVE) LEGEND: R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect; -n = value after reset Table 27.

  • Page 74: Mdio Link Status Change Interrupt (Unmasked) Register (Linkintraw)

    MDIO Registers MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) The MDIO link status change interrupt (unmasked) register (LINKINTRAW) is shown in described in Table Figure 31. MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) LEGEND: R = Read only; R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect; -n = value after reset Table 29.

  • Page 75: Mdio Link Status Change Interrupt (Masked) Register (Linkintmasked)

    www.ti.com MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) The MDIO link status change interrupt (masked) register (LINKINTMASKED) is shown in described in Table Figure 32. MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) LEGEND: R = Read only; R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect; -n = value after reset Table 30.

  • Page 76: Mdio User Command Complete Interrupt (Unmasked) Register (Userintraw)

    MDIO Registers MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) The MDIO user command complete interrupt (unmasked) register (USERINTRAW) is shown in Figure 33 and described in Figure 33. MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) LEGEND: R = Read only; R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect; -n = value after reset Table 31.

  • Page 77: Mdio User Command Complete Interrupt (Masked) Register (Userintmasked)

    www.ti.com MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) The MDIO user command complete interrupt (masked) register (USERINTMASKED) is shown in Figure 34 and described in Figure 34. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) LEGEND: R = Read only; R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect; -n = value after reset Table 32.

  • Page 78: Mdio User Command Complete Interrupt Mask Set Register (Userintmaskset)

    MDIO Registers MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) The MDIO user command complete interrupt mask set register (USERINTMASKSET) is shown in Figure 35 and described in Figure 35. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) LEGEND: R = Read only;...

  • Page 79: Mdio User Command Complete Interrupt Mask Clear Register (Userintmaskclear)

    www.ti.com 4.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) The MDIO user command complete interrupt mask clear register (USERINTMASKCLEAR) is shown in Figure 36 and described in Figure 36. MDIO User Command Complete Interrupt Mask Clear Register LEGEND: R = Read only; R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect; -n = value after reset Table 34.

  • Page 80: Mdio User Access Register 0 (Useraccess0)

    MDIO Registers 4.11 MDIO User Access Register 0 (USERACCESS0) The MDIO user access register 0 (USERACCESS0) is shown in Figure 37. MDIO User Access Register 0 (USERACCESS0) WRITE Reserved R/W1S-0 R/W-0 R/W-0 LEGEND: R = Read only; R/W = Read/Write; W1S = Write 1 to set, write of 0 has no effect; -n = value after reset Table 35.

  • Page 81: Mdio User Phy Select Register 0 (Userphysel0)

    www.ti.com 4.12 MDIO User PHY Select Register 0 (USERPHYSEL0) The MDIO user PHY select register 0 (USERPHYSEL0) is shown in Table Figure 38. MDIO User PHY Select Register 0 (USERPHYSEL0) Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 36.

  • Page 82: Mdio User Access Register 1 (Useraccess1)

    MDIO Registers 4.13 MDIO User Access Register 1 (USERACCESS1) The MDIO user access register 1 (USERACCESS1) is shown in Figure 39. MDIO User Access Register 1 (USERACCESS1) WRITE Reserved R/W1S-0 R/W-0 R/W-0 LEGEND: R = Read only; R/W = Read/Write; W1S = Write 1 to set, write of 0 has no effect; -n = value after reset Table 37.

  • Page 83: Mdio User Phy Select Register 1 (Userphysel1)

    www.ti.com 4.14 MDIO User PHY Select Register 1 (USERPHYSEL1) The MDIO user PHY select register 1 (USERPHYSEL1) is shown in Table Figure 40. MDIO User PHY Select Register 1 (USERPHYSEL1) Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 38.

  • Page 84: Ethernet Media Access Controller (Emac) Registers

    Ethernet Media Access Controller (EMAC) Registers Ethernet Media Access Controller (EMAC) Registers Table 39 lists the memory-mapped registers for the EMAC. See the device-specific data manual for the memory address of these registers. Table 39. Ethernet Media Access Controller (EMAC) Registers Offset Acronym TXIDVER...
  • Page 85 www.ti.com Table 39. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym 164h MACSTATUS 168h EMCONTROL 16Ch FIFOCONTROL 170h MACCONFIG 174h SOFTRESET 1D0h MACSRCADDRLO 1D4h MACSRCADDRHI 1D8h MACHASH1 1DCh MACHASH2 1E0h BOFFTEST 1E4h TPACETEST 1E8h RXPAUSE 1ECh TXPAUSE 500h MACADDRLO 504h MACADDRHI 508h...
  • Page 86 Ethernet Media Access Controller (EMAC) Registers Table 39. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym 678h RX6CP 67Ch RX7CP 200h RXGOODFRAMES 204h RXBCASTFRAMES 208h RXMCASTFRAMES 20Ch RXPAUSEFRAMES 210h RXCRCERRORS 214h RXALIGNCODEERRORS 218h RXOVERSIZED 21Ch RXJABBER 220h RXUNDERSIZED 224h RXFRAGMENTS 228h RXFILTERED...

  • Page 87: Transmit Identification And Version Register (Txidver)

    www.ti.com Transmit Identification and Version Register (TXIDVER) The transmit identification and version register (TXIDVER) is shown in Table Figure 41. Transmit Identification and Version Register (TXIDVER) TXMAJORVER R-0Ah LEGEND: R = Read only; -n = value after reset Table 40. Transmit Identification and Version Register (TXIDVER) Field Descriptions Field Value Description...

  • Page 88: Transmit Teardown Register (Txteardown)

    Ethernet Media Access Controller (EMAC) Registers Transmit Teardown Register (TXTEARDOWN) The transmit teardown register (TXTEARDOWN) is shown in Figure 43. Transmit Teardown Register (TXTEARDOWN) LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 42. Transmit Teardown Register (TXTEARDOWN) Field Descriptions Field Value Description...

  • Page 89: Receive Identification And Version Register (Rxidver)

    www.ti.com Receive Identification and Version Register (RXIDVER) The receive identification and version register (RXIDVER) is shown in Table Figure 44. Receive Identification and Version Register (RXIDVER) RXMAJORVER R-0Ah LEGEND: R = Read only; -n = value after reset Table 43. Receive Identification and Version Register (RXIDVER) Field Descriptions Field Value Description...

  • Page 90: Receive Teardown Register (Rxteardown)

    Ethernet Media Access Controller (EMAC) Registers Receive Teardown Register (RXTEARDOWN) The receive teardown register (RXTEARDOWN) is shown in Figure 46. Receive Teardown Register (RXTEARDOWN) LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 45. Receive Teardown Register (RXTEARDOWN) Field Descriptions Field Value Description...

  • Page 91: Transmit Interrupt Status (Unmasked) Register (Txintstatraw)

    www.ti.com Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) The transmit interrupt status (unmasked) register (TXINTSTATRAW) is shown in described in Table Figure 47. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) TX7PEND TX6PEND TX5PEND LEGEND: R = Read only; -n = value after reset Table 46.

  • Page 92: Transmit Interrupt Status (Masked) Register (Txintstatmasked)

    Ethernet Media Access Controller (EMAC) Registers Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) The transmit interrupt status (masked) register (TXINTSTATMASKED) is shown in described in Table Figure 48. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) TX7PEND TX6PEND TX5PEND LEGEND: R = Read only; -n = value after reset Table 47.

  • Page 93: Transmit Interrupt Mask Set Register (Txintmaskset)

    www.ti.com Transmit Interrupt Mask Set Register (TXINTMASKSET) The transmit interrupt mask set register (TXINTMASKSET) is shown in Table Figure 49. Transmit Interrupt Mask Set Register (TXINTMASKSET) TX7MASK TX6MASK TX5MASK R/W1S-0 R/W1S-0 R/W1S-0 LEGEND: R = Read only; R/W = Read/Write; W1S = Write 1 to set, write of 0 has no effect; -n = value after reset Table 48.

  • Page 94: Transmit Interrupt Mask Clear Register (Txintmaskclear)

    Ethernet Media Access Controller (EMAC) Registers 5.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) The transmit interrupt mask clear register (TXINTMASKCLEAR) is shown in Table Figure 50. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) TX7MASK TX6MASK TX5MASK R/W1C-0 R/W1C-0 R/W1C-0 LEGEND: R = Read only; R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect; -n = value after reset Table 49.

  • Page 95: Mac Input Vector Register (Macinvector)

    www.ti.com 5.11 MAC Input Vector Register (MACINVECTOR) The MAC input vector register (MACINVECTOR) is shown in Figure 51. MAC Input Vector Register (MACINVECTOR) Reserved STATPEND RXTHRESHPEND LEGEND: R = Read only; -n = value after reset Table 50. MAC Input Vector Register (MACINVECTOR) Field Descriptions Field Value 31-28...

  • Page 96: Receive Interrupt Status (Unmasked) Register (Rxintstatraw)

    Ethernet Media Access Controller (EMAC) Registers 5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) The receive interrupt status (unmasked) register (RXINTSTATRAW) is shown in described in Table Figure 53. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) RX7PEND RX6PEND RX5PEND LEGEND: R = Read only; -n = value after reset Table 52.

  • Page 97: Receive Interrupt Status (Masked) Register (Rxintstatmasked)

    www.ti.com 5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) The receive interrupt status (masked) register (RXINTSTATMASKED) is shown in described in Table Figure 54. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) RX7PEND RX6PEND RX5PEND LEGEND: R = Read only; -n = value after reset Table 53.

  • Page 98: Receive Interrupt Mask Set Register (Rxintmaskset)

    Ethernet Media Access Controller (EMAC) Registers 5.15 Receive Interrupt Mask Set Register (RXINTMASKSET) The receive interrupt mask set register (RXINTMASKSET) is shown in Table Figure 55. Receive Interrupt Mask Set Register (RXINTMASKSET) RX7MASK RX6MASK RX5MASK R/W1S-0 R/W1S-0 R/W1S-0 LEGEND: R = Read only; R/W = Read/Write; W1S = Write 1 to set, write of 0 has no effect; -n = value after reset Table 54.

  • Page 99: Receive Interrupt Mask Clear Register (Rxintmaskclear)

    www.ti.com 5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) The receive interrupt mask clear register (RXINTMASKCLEAR) is shown in Table Figure 56. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) RX7MASK RX6MASK RX5MASK R/W1C-0 R/W1C-0 R/W1C-0 LEGEND: R = Read only; R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect; -n = value after reset Table 55.

  • Page 100: Mac Interrupt Status (Unmasked) Register (Macintstatraw)

    Ethernet Media Access Controller (EMAC) Registers 5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) The MAC interrupt status (unmasked) register (MACINTSTATRAW) is shown in described in Table Figure 57. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) LEGEND: R = Read only; -n = value after reset Table 56.

  • Page 101: Mac Interrupt Mask Set Register (Macintmaskset)

    www.ti.com 5.19 MAC Interrupt Mask Set Register (MACINTMASKSET) The MAC interrupt mask set register (MACINTMASKSET) is shown in Table Figure 59. MAC Interrupt Mask Set Register (MACINTMASKSET) LEGEND: R = Read only; R/W = Read/Write; W1S = Write 1 to set, write of 0 has no effect; -n = value after reset Table 58.

  • Page 102: Receive Multicast/Broadcast/Promiscuous Channel Enable Register (Rxmbpenable)

    Ethernet Media Access Controller (EMAC) Registers 5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) The receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE) is shown in Figure 61 and described in Figure 61. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Reserved RXPASSCRC RXQOSEN R/W-0 R/W-0 RXCSFEN RXCEFEN...
  • Page 103 www.ti.com Table 60. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Value Description RXCEFEN Receive copy error frames enable bit. Enables frames containing errors to be transferred to memory. The appropriate error bit will be set in the frame EOP buffer descriptor. Frames containing errors are filtered.
  • Page 104 Ethernet Media Access Controller (EMAC) Registers Table 60. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Value Description RXMULTCH 0-7h Receive multicast channel select Select channel 0 to receive multicast frames Select channel 1 to receive multicast frames Select channel 2 to receive multicast frames Select channel 3 to receive multicast frames Select channel 4 to receive multicast frames Select channel 5 to receive multicast frames...

  • Page 105: Receive Unicast Enable Set Register (Rxunicastset)

    www.ti.com 5.22 Receive Unicast Enable Set Register (RXUNICASTSET) The receive unicast enable set register (RXUNICASTSET) is shown in Table Figure 62. Receive Unicast Enable Set Register (RXUNICASTSET) RXCH7EN RXCH6EN RXCH5EN R/W1S-0 R/W1S-0 R/W1S-0 LEGEND: R = Read only; R/W = Read/Write; W1S = Write 1 to set, write of 0 has no effect; -n = value after reset Table 61.

  • Page 106: Receive Unicast Clear Register (Rxunicastclear)

    Ethernet Media Access Controller (EMAC) Registers 5.23 Receive Unicast Clear Register (RXUNICASTCLEAR) The receive unicast clear register (RXUNICASTCLEAR) is shown in Table Figure 63. Receive Unicast Clear Register (RXUNICASTCLEAR) RXCH7EN RXCH6EN RXCH5EN R/W1C-0 R/W1C-0 R/W1C-0 LEGEND: R = Read only; R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect; -n = value after reset Table 62.

  • Page 107: Receive Maximum Length Register (Rxmaxlen)

    www.ti.com 5.24 Receive Maximum Length Register (RXMAXLEN) The receive maximum length register (RXMAXLEN) is shown in Figure 64. Receive Maximum Length Register (RXMAXLEN) LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 63. Receive Maximum Length Register (RXMAXLEN) Field Descriptions Field Value 31-16...

  • Page 108: Receive Filter Low Priority Frame Threshold Register (Rxfilterlowthresh)

    Ethernet Media Access Controller (EMAC) Registers 5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) The receive filter low priority frame threshold register (RXFILTERLOWTHRESH) is shown in and described in Table Figure 66. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Reserved LEGEND: R = Read only;...

  • Page 109: Receive Channel 0-7 Free Buffer Count Register (Rxnfreebuffer)

    www.ti.com 5.28 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER) The receive channel 0-7 free buffer count register (RXnFREEBUFFER) is shown in described in Table Figure 68. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) LEGEND: R = Read only; WI = Write to increment; -n = value after reset Table 67.

  • Page 110: Mac Control Register (Maccontrol)

    Ethernet Media Access Controller (EMAC) Registers 5.29 MAC Control Register (MACCONTROL) The MAC control register (MACCONTROL) is shown in Figure 69. MAC Control Register (MACCONTROL) Reserved RXOFFLENBLOCK RXOWNERSHIP R/W-0 TXPACE GMIIEN R/W-0 R/W-0 R/W-0 LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 68.
  • Page 111 www.ti.com Table 68. MAC Control Register (MACCONTROL) Field Descriptions (continued) Field Value GMIIEN TXFLOWEN RXBUFFERFLOWEN Reserved LOOPBACK FULLDUPLEX SPRUEQ6 – December 2007 Submit Documentation Feedback Ethernet Media Access Controller (EMAC) Registers Description GMII enable bit. GMII RX and TX are held in reset. GMII RX and TX are enabled for receive and transmit.

  • Page 112: Mac Status Register (Macstatus)

    Ethernet Media Access Controller (EMAC) Registers 5.30 MAC Status Register (MACSTATUS) The MAC status register (MACSTATUS) is shown in IDLE Reserved RXERRCODE Reserved LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 69. MAC Status Register (MACSTATUS) Field Descriptions Field Value Description...
  • Page 113 www.ti.com Table 69. MAC Status Register (MACSTATUS) Field Descriptions (continued) Field Value Description 10-8 RXERRCH 0-3h Receive host error channel. These bits indicate which receive channel the host error occurred on. This field is cleared to 0 on a host read. The host error occurred on receive channel 0 The host error occurred on receive channel 1 The host error occurred on receive channel 2...

  • Page 114: Emulation Control Register (Emcontrol)

    Ethernet Media Access Controller (EMAC) Registers 5.31 Emulation Control Register (EMCONTROL) The emulation control register (EMCONTROL) is shown in Figure 71. Emulation Control Register (EMCONTROL) LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 70. Emulation Control Register (EMCONTROL) Field Descriptions Field Value Description...

  • Page 115: Mac Configuration Register (Macconfig)

    www.ti.com 5.33 MAC Configuration Register (MACCONFIG) The MAC configuration register (MACCONFIG) is shown in Figure 73. MAC Configuration Register (MACCONFIG) TXCELLDEPTH R-18h ADDRESSTYPE R-2h LEGEND: R = Read only; -n = value after reset Table 72. MAC Configuration Register (MACCONFIG) Field Descriptions Field Value Description...

  • Page 116: Mac Source Address Low Bytes Register (Macsrcaddrlo)

    Ethernet Media Access Controller (EMAC) Registers 5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) The MAC source address low bytes register (MACSRCADDRLO) is shown in Table Figure 75. MAC Source Address Low Bytes Register (MACSRCADDRLO) MACSRCADDR0 R/W-0 LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 74.

  • Page 117: Mac Hash Address Register 1 (Machash1)

    www.ti.com 5.37 MAC Hash Address Register 1 (MACHASH1) The MAC hash registers allow group addressed frames to be accepted on the basis of a hash function of the address. The hash function creates a 6-bit data value (Hash_fun) from the 48-bit destination address (DA) as follows: Hash_fun(0)=DA(0) XOR DA(6) XOR DA(12) XOR DA(18) XOR DA(24) XOR DA(30) XOR DA(36) XOR DA(42);...

  • Page 118: Back Off Test Register (Bofftest)

    Ethernet Media Access Controller (EMAC) Registers 5.39 Back Off Test Register (BOFFTEST) The back off test register (BOFFTEST) is shown in Figure 79. Back Off Random Number Generator Test Register (BOFFTEST) Reserved COLLCOUNT Reserved LEGEND: R = Read only; -n = value after reset Table 78.

  • Page 119: Receive Pause Timer Register (Rxpause)

    www.ti.com 5.41 Receive Pause Timer Register (RXPAUSE) The receive pause timer register (RXPAUSE) is shown in Figure 81. Receive Pause Timer Register (RXPAUSE) LEGEND: R = Read only; -n = value after reset Table 80. Receive Pause Timer Register (RXPAUSE) Field Descriptions Field Value Description...

  • Page 120: Mac Address Low Bytes Register (Macaddrlo)

    Ethernet Media Access Controller (EMAC) Registers 5.43 MAC Address Low Bytes Register (MACADDRLO) The MAC address low bytes register used in address matching (MACADDRLO), is shown in and described in Table Figure 83. MAC Address Low Bytes Register (MACADDRLO) Reserved MACADDR0 R/W-0 LEGEND: R/W = Read/Write;...

  • Page 121: Mac Address High Bytes Register (Macaddrhi)

    www.ti.com 5.44 MAC Address High Bytes Register (MACADDRHI) The MAC address high bytes register (MACADDRHI) is shown in Figure 84. MAC Address High Bytes Register (MACADDRHI) MACADDR2 R/W-0 MACADDR4 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset Table 83. MAC Address High Bytes Register (MACADDRHI) Field Descriptions Field Value Description...

  • Page 122: Transmit Channel 0-7 Dma Head Descriptor Pointer Register (Txnhdp)

    Ethernet Media Access Controller (EMAC) Registers 5.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TXnHDP) The transmit channel 0-7 DMA head descriptor pointer register (TXnHDP) is shown in described in Table Figure 86. Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) LEGEND: R/W = Read/Write;...

  • Page 123: Transmit Channel 0-7 Completion Pointer Register (Txncp)

    www.ti.com 5.48 Transmit Channel 0-7 Completion Pointer Register (TXnCP) The transmit channel 0-7 completion pointer register (TXnCP) is shown in Table Figure 88. Transmit Channel n Completion Pointer Register (TXnCP) LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset Table 87.

  • Page 124: 5.50 Network Statistics Registers

    Ethernet Media Access Controller (EMAC) Registers 5.50 Network Statistics Registers The EMAC has a set of statistics that record events associated with frame traffic. The statistics values are cleared to zero 38 clocks after the rising edge of reset. When the GMIIEN bit in the MACCONTROL register is set, all statistics registers (see subtracted from the register value with the result stored in the register.
  • Page 125 www.ti.com 5.50.4 Pause Receive Frames Register (RXPAUSEFRAMES) The total number of IEEE 802.3X pause frames received by the EMAC (whether acted upon or not). A pause frame is defined as having all of the following: Contained any unicast, broadcast, or multicast address Contained the length/type field value 88.08h and the opcode 0001h Was of length 64 to RXMAXLEN bytes inclusive Had no CRC error, alignment error, or code error...
  • Page 126 Ethernet Media Access Controller (EMAC) Registers Section 2.5.5 for definitions of alignment, code, and CRC errors. Overruns have no effect on this statistic. 5.50.8 Receive Jabber Frames Register (RXJABBER) The total number of jabber frames received on the EMAC. A jabber frame is defined as having all of the following: Was any data or MAC control frame that matched a unicast, broadcast, or multicast address, or matched due to promiscuous mode...
  • Page 127 www.ti.com To determine the number of receive frames discarded by the EMAC for any reason, sum the following statistics (promiscuous mode disabled): Receive fragments Receive undersized frames Receive CRC errors Receive alignment/code errors Receive jabbers Receive overruns Receive filtered frames This may not be an exact count because the receive overruns statistic is independent of the other statistics, so if an overrun occurs at the same time as one of the other discard reasons, then the above sum double-counts that frame.
  • Page 128 Ethernet Media Access Controller (EMAC) Registers 5.50.16 Multicast Transmit Frames Register (TXMCASTFRAMES) The total number of good multicast frames transmitted on the EMAC. A good multicast frame is defined as having all of the following: Any data or MAC control frame destined for any multicast address other than FF-FF-FF-FF-FF-FFh Was of any length Had no late or excessive collisions, no carrier loss, and no underrun 5.50.17 Pause Transmit Frames Register (TXPAUSEFRAMES)
  • Page 129 www.ti.com CRC errors have no effect on this statistic. 5.50.21 Transmit Multiple Collision Frames Register (TXMULTICOLL) The total number of frames transmitted on the EMAC that experienced multiple collisions. Such a frame is defined as having all of the following: Was any data or MAC control frame destined for any unicast, broadcast, or multicast address Was any size Had no carrier loss and no underrun...
  • Page 130 Ethernet Media Access Controller (EMAC) Registers 5.50.26 Transmit Octet Frames Register (TXOCTETS) The total number of bytes in all good frames transmitted on the EMAC. A good frame is defined as having all of the following: Any data or MAC control frame that was destined for any unicast, broadcast, or multicast address Was any length Had no late or excessive collisions, no carrier loss, and no underrun 5.50.27 Transmit and Receive 64 Octet Frames Register (FRAME64)
  • Page 131 www.ti.com 5.50.31 Transmit and Receive 512 to 1023 Octet Frames Register (FRAME512T1023) The total number of 512-byte to 1023-byte frames received and transmitted on the EMAC. Such a frame is defined as having all of the following: Any data or MAC control frame that was destined for any unicast, broadcast, or multicast address Did not experience late collisions, excessive collisions, underrun, or carrier sense error Was 512-bytes to 1023-bytes long CRC errors, alignment/code errors, and overruns do not affect the recording of frames in this statistic.
  • Page 132 Ethernet Media Access Controller (EMAC) Registers 5.50.35 Receive FIFO or DMA Middle of Frame Overruns Register (RXMOFOVERRUNS) The total number of frames received on the EMAC that had either a FIFO or DMA middle of frame (MOF) overrun. An MOF overrun frame is defined as having all of the following: Was any data or MAC control frame that matched a unicast, broadcast, or multicast address, or matched due to promiscuous mode Was of any size (including less than 64-byte and greater than RXMAXLEN-byte frames)

  • Page 133: Appendix A Glossary

    Host— The host is an intelligent system resource that configures and manages each communications control module. The host is responsible for allocating memory, initializing all data structures, and responding to port (EMAC) interrupts. In this document, host refers to the TMS320DM646x device.

  • Page 134: Physical Layer Definitions

    Appendix A Link— The transmission path between any two instances of generic cabling. Multicast MAC Address— A class of MAC address that sends a packet to potentially more than one recipient. A group address is specified by setting the LSB of the first MAC address byte to 1. Thus, 01h-02h-03h-04h-05h-06h is a valid multicast address.

  • Page 135: Important Notice

    TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers amplifier.ti.com...

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