Texas Instruments OMAP5912 Reference Manual page 220

Clock Generation and Reset Management
Table 80. DSP Clock Reset Status Register (DSP_SYSST) (Continued)
Bit Name
3 DSP_ARM_RST
2 ARM_WDRST
1 GLOB_SWRST
0 DSP_WDRST
162 OMAP3.2 Subsystem
Base Address = 0xE100 8000 or 0x008000, Offset = 0x18
Function
Used by the DSP to hold the MPU in reset. This is for
test and debug purposes only. Not for users.
0: The MPU is enabled.
1: Reset the MPU.
Indicates whether or not the reset has been asserted
due to a MPU timer/watchdog underflow.
This bit cannot be written to logic 1 from the TIPB
interface.
0: An MPU timer/watchdog underflow has not
occurred.
1: An MPU timer/watchdog underflow has generated
the reset.
Indicates whether or not the reset has been asserted
due to global software reset. This bit cannot be
written to logic 1 from the TIPB interface.
0: A global software reset has not been requested.
1: A global software reset has been requested.
Indicates whether or not the reset has been asserted
due to DSP timer/watchdog underflow. This bit cannot
be written to logic 1 from the TIPB interface.
0: A DSP timer/watchdog underflow has not occurred.
1: A DSP timer/watchdog underflow has generated
the reset.
R/W Reset
R/W 0
R/C 0
R/C 0
R/C 0
SPRU749A