Texas Instruments OMAP5912 Reference Manual page 294

Table 4. Flush Line Register 0 (FLR0)
Bit Name
15:0 Line address
Table 5. Flush Line Register 1 (FLR1)
Bit Name
15:8 Reserved
7:0 Line address
Table 6. I-Cache N-Way Register (NWCR)
Bit Name
15:5 Reserved
4:2 Way size
1 Flush
0 Enable
Table 7. I-Cache Status Register (ISR)
Bit Name
15:3 Reserved
2 I-cache_Enable
SPRU750A
Description
Low 16 bits of line address: byte address
This address is used to select the line when a flush line occurs.
Description
High 8 bits of line address: byte address
This address is used to select the line when a flush line occurs.
Description
Way size = 011: 8K bytes: Way size configuration must not be set to
any other value (reserved value).
N-way flush mask:
0: N-way not flushed by the GL_CACHECLR_TR input
1: N-way flushed by the GL_CACHECLR_TR input (all the line valid
bits are invalidated)
N-way enable mask:
0: N-way not enabled when CAEN = 1
1: N-way enabled when CAEN = 1
Description
Disable/enable I-cache:
0: I-cache disabled
1: I-cache enabled
This bit must be queried to ensure that the i-cache is enabled before
writing to the ramset TAG register.
DSP Memory
Access
R/W
Access
R
R/W
Access
R
R/W
R/W
R/W
Access
R
R
DSP Subsystem 31